WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 351

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
Note:
Note:
Note:
10.2.6.12
WTHRESH controls the write-back of processed transmit descriptors. This threshold
refers to the number of transmit descriptors in the on-chip buffer that are ready to be
written back to host memory. In the absence of external events (explicit flushes), the
write back occurs only after at least WTHRESH descriptors are available for write back.
For any WTHRESH value other than zero - packet and absolute timers must get a non-
zero value for the WTHRESH feature to take affect.
Since the default value for write-back threshold is zero, descriptors are normally
written back as soon as they are processed. WTHRESH must be a non-zero value to
take advantage of the write-back bursting capabilities of the 82574.
Since write-back of transmit descriptors is optional (under the control of RS bit in the
descriptor), not all processed descriptors are counted with respect to WTHRESH.
Descriptors start accumulating after a descriptor with RS is set. Furthermore, with
transmit descriptor bursting enabled, some descriptors are written back that did not
have RS set in their respective descriptors.
Leaving this value at its default causes descriptor processing to be similar to previous
devices.
As descriptors are transmitted the number of descriptors waiting in the transmit
descriptor queue decreases as noted by the transmit descriptor head and tail positions
in the circular queue. When the number of waiting descriptors drops to LWTHRESH (the
head and tail positions are sufficiently close to one another) an interrupt is asserted.
LWTHRESH controls the number of descriptors in transmit ring, at which a transmit
descriptor-low interrupt (ICR.TXD_LOW) is reported. This might enable software to
operate more efficiently by maintaining a continuous addition of transmit work,
interrupting only when the hardware nears completion of all submitted work.
LWTHRESH specifies a multiple of eight descriptors. An interrupt is asserted when the
number of descriptors available transitions from (threshold level=8*LWTHRESH)+1 ‡
(threshold level=8*LWTHRESH). Setting this value to zero disables this feature.
Transmit Absolute Interrupt Delay Value-TADV (0x0382C; RW)
IDV
Reserved
• Possible values:
Field
— GRAN = 1b (descriptor granularity):
— PTHRESH = 0..47
— WTHRESH = 0..63
— HTHRESH = 0..63
— GRAN = 0 (cacheline granularity):
— PTHRESH = 0..3 (for 16 descriptors cacheline - 256 bytes)
— WTHRESH = 0..3
— HTHRESH = 0..4
15:0
31:16
Bit(s)
0x0
0x0
Initial
Value
Interrupt Delay Value
Counts in units of 1.024 s. (0b = disabled).
Reads as 0x0. Should be written to 0x0 for future compatibility.
Description
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