WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 272

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.1.6.1.4
9.1.6.1.5
272
Device CAP, Offset 0xE4, (RO)
This register identifies the PCIe device specific capabilities. It is a read-only register.
Device Control, Offset 0xE8, (RW)
This register controls PCIe specific parameters.
2:0
4:3
5
8:6
11:9
12
13
14
15
17:16
25:18
27:26
31:28
0
1
2
3
4
Bits
Bits
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
R/W
R/W
001b
00b
0b
011b
110b
0b
0b
0b
1b
00b
0x0
00b
0000b
0b
0b
0b
0b
1b
Default
Default
Max Payload Size Supported
This field indicates the maximum payload that the device can support for
TLPs. It is loaded from the NVM PCIe Init Configuration 3 word 0x1A (bit 8)
with a default value of 256 bytes.
Phantom Function Supported
Not supported by the 82574.
Extended Tag Field Supported
Max supported size of the Tag field. The 82574L supports a 5-bit Tag field.
End-Point L0s Acceptable Latency
This field indicates the acceptable latency that the 82574 can withstand due
to the transition from L0s state to the L0 state. The value is loaded from the
NVM PCIe Init Configuration 1 word 0x18.
End-Point L1 Acceptable Latency
This field indicates the acceptable latency that the 82574 can withstand due
to the transition from L1 state to the L0 state. The value is loaded from the
NVM PCIe Init Configuration 1 word 0x18.
Attention Button Present
Hardwired in the 82574 to 0b.
Attention Indicator Present
Hardwired in the 82574 to 0b.
Power Indicator Present
Hardwired in the 82574 to 0b.
Role Based Error Reporting
Hardwired in the 82574 to 1b.
Reserved, set to 00b
Slot Power Limit Value
Used in upstream ports only. Hardwired in the 82574 to 0x00.
Slot Power Limit Scale
Used in upstream ports only. Hardwired in the 82574 to 0b.
Reserved
Correctable Error Reporting Enable
Enable error report.
Non-Fatal Error Reporting Enable
Enable error report.
Fatal Error Reporting Enable
Enable error report.
Unsupported Request Reporting Enable
Enable error report.
Enable Relaxed Ordering
If this bit is set, the device is permitted to set the Relaxed Ordering bit in the
attribute field of write transactions that do not need strong ordering. For
more details, also see register CTRL_EXT bit RO_DIS.
82574 GbE Controller—Programing Interface
Description
Description