WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 293

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
Note:
10.2.2
10.2.2.1
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Category
0x03428
0x03430
0x10000 -
0x17FFF
0x01008
Certain registers maintain an alias address designed for backward compatibility with
software written for previous devices. For these registers, the alias address is shown in
Table
alias offset. It is recommended that software written solely for the 82574, use the new
address offset.
General Register Descriptions
Device Control Register - CTRL (0x00000 / 0x00004; RW)
Offset
FD
Reserved
GIO Master
Disable
Reserved
Reserved
ASDE
SLU
Reserved
Field
79. Those registers can be accessed by software at either the new offset or the
N/A
N/A
N/A
N/A
Offset
Alias
0
1
2
3
4
5
6
7
Bit(s)
TDFTS
TDFPC
PBM
PBS
Abbreviation
1b
0b
0b
1b
0b
0b
0b
0b
Initial
Value
1
1
1
Full Duplex
0b = Half duplex
1b = Full duplex. Controls the MAC duplex setting when explicitly set
by software.
Reserved
Write as 0b for future compatibility.
When set, the 82574 blocks new master requests, including
manageability requests, by this function. Once no master requests
are pending by this function, the GIO Master Enable Status bit is set.
Reserved
Set to 1b.
Reserved
Write as 0b for future compatibility.
Auto-Speed Detection Enable
When set to 1b, the MAC ignores the speed indicated by the PHY and
attempts to automatically detect the resolved speed of the link and
configure itself appropriately.
This bit must be set to 0b in the 82574.
Set Link Up
The Set Link Up bit MUST be set to 1b to permit the MAC to recognize
the link signal from the PHY, which indicates the PHY has gotten the
link up, and to receive and transmit data.
See
link configuration in the various modes.
Set link up is normally initialized to 0b. However, if the APM Enable bit
is set in the NVM then it is initialized to 1b.
Reserved.
Must be set to 0b.
Transmit Data FIFO Tail Saved Register
Transmit Data FIFO Packet Count
Packet Buffer Memory
Packet Buffer Size
Section 3.2.3
for more information about auto-negotiation and
Name
Description
RW
RW
RW
RW
RW
page 415
page 415
page 415
page 416
Link to
Page
293