WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 453

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Design Considerations—82574 GbE Controller
13.6
SMBus and NC-SI
SMBus and NC-SI are optional interfaces for pass-through and/or configuration traffic
between the MC and the 82574. See
This section describes the hardware implementation requirements necessary to meet
the NC-SI physical layer standard. Board-level design requirements are included for
connecting the 82574 Ethernet solution to an external MC. The layout and connectivity
requirements are addressed in low-level detail. This section, in conjunction with the
Network Controller Sideband Interface (NC-SI) Specification Version 1.0 RMII
Specification, also provides the complete board-level requirements for the NC-SI
solution.
The 82574’s on-board System Management Bus (SMBus) port enables network
manageability implementations required for remote control and alerting via the LAN.
With SMBus, management packets can be routed to or from an MC. Enhanced pass-
through capabilities also enable system remote control over standardized interfaces.
Also included is a new manageability interface, NC-SI that supports the DMTF preOS
sideband protocol. An internal management interface called MDIO enables the MAC
(and software) to monitor and control the PHY.
3. Excessive distance between the Ethernet silicon and the magnetics. Long traces on
4. Routing any other trace parallel to and close to one of the differential traces.
5. Routing one pair of differential traces too close to another pair of differential traces.
6. Use of a low-quality magnetics module.
7. Re-use of an out-of-date physical layer schematic in a Ethernet silicon design. The
8. Incorrect differential trace impedances. It is important to have ~100  impedance
FR4 fiberglass epoxy substrate will attenuate the analog signals. In addition, any
impedance mismatch in the traces will be aggravated if they are longer than the
four inch guideline.
Crosstalk getting onto the receive channel will cause degraded long cable BER.
Crosstalk getting onto the transmit channel can cause excessive EMI emissions and
can cause poor transmit BER on long cables. At a minimum, other signals should be
kept 0.3 inches from the differential traces.
After exiting the Ethernet silicon, the trace pairs should be kept 0.3 inches or more
away from the other trace pairs. The only possible exceptions are in the vicinities
where the traces enter or exit the magnetics, the RJ-45 connector, and the
Ethernet silicon.
terminations and decoupling can be different from one PHY to another.
between the two traces within a differential pair. This becomes even more
important as the differential traces become longer. To calculate differential
impedance, many impedance calculators only multiply the single-ended impedance
by two. This does not take into account edge-to-edge capacitive coupling between
the two traces. When the two traces within a differential pair are kept close to each
other, the edge coupling can lower the effective differential impedance by 5  to
20 . Short traces have fewer problems if the differential impedance is slightly off
target.
section 3.4
and
section 3.5
for more details.
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