WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 482

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

482
Clock Source
(Crystal Option)
NVM
SMBus
Section
Use 25 MHz 30 ppm accuracy @ 25 °C crystal.
Avoid components that introduce jitter.
Connect two load capacitors to crystal; one on
XTAL1 and one on XTAL2. Use 27 pF
capacitors as a starting point, but be prepared
to change the value based on testing.
Use 0.1 F decoupling capacitor.
If SPI Flash is used, connect pin 38 (NVMT) to
ground through a 1 K resistor. If an SPI
EEPROM is used, connect pin 38 (NVMT) to 3.3
V dc through a 1 K resistor.
The NVM must be powered from auxiliary
power.
Check connections to NVM_CS_N, NVM_SK,
NVM_SI, NVM_SO.
For best performance, each 82574 should
have it's own dedicated SMBus link to the
SMBus master device.
If SMBus is not used, connect pull-up resistors
to SMB_CLK, SMB_DAT, and SMB_ALRT_N.
If SMBus is used, there should be pull-up
resistors on SMB_DAT, SMB_ALRT_N and
SMB_CLK somewhere on the board.
Check Items
82574 GbE Controller—Board Layout and Schematic Checklists
Parallel resonant crystals are required. The Cload
should be 18 pF. Specify Equivalent Series Resistance
(ESR) to be 50  or less.
Capacitance affects accuracy of the frequency. Must be
matched to crystal specifications, including estimated
trace capacitance in calculation.
Use capacitors with low ESR (types C0G or NPO, for
example). Refer to the design considerations section of
the datasheet and the Intel Ethernet Controllers Timing
Device Selection Guide for more information.
Applies to EEPROM or Flash devices.
Ensure pull-ups are connected to auxiliary power.
The NVM is read when the system is powered on even
before main power is available.
Pins on the 82574 are connected to same named pins
on the NVM. (NVM_SI connects to SI on NVM.
NVM_SO connects to SO on NVM.)
The 82574 allows for multiple devices on a SMBus link;
however, the SMBus has a very limited throughput.
Using multiple devices further limits throughput.
The 82574 has errata with respect to SMBus ARP when
multiple slave devices are used. Using only a single
device per bus avoids these errata.
10 K pull-ups are reasonable values. Ensure pull-ups
are connected to auxiliary power. This prevents noise
on these pins from causing problems with device
operation.
SMBus signals are open-drain. Ensure pull-ups are
connected to auxiliary power.
Remarks