WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 23

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Interface—82574 GbE Controller
2.3.3
Table 9.
Note:
2.3.4
Table 10.
System Management Bus (SMBus) Interface
SMBus Interface
If the SMBus is disconnected, an external pull-up should be used for these pins, unless
it is guaranteed that manageability is disabled in the 82574.
NC-SI and Testability
NC-SI and Testability
SMB_DAT
SMB_CLK
SMB_ALRT_N
NC_SI_CLK_IN
NC_SI_CRS_DV
NC_SI_RXD0
NC_SI_RXD1
NC_SI_TX_EN
NC_SI_TXD0
NC_SI_TXD1
TEST_EN
Symbol
Symbol
2
3
6
5
7
9
8
29
Lead #
36
34
35
Lead #
NC-SI_
in
NC-SI_
out
NC-SI_
out
NC-SI_
out
NC-SI_
in
NC-SI_
in
NC-SI_
in
In
Type
T/s, o/d
T/s, o/d
T/s, o/d
Type
Input
Output
Output
Output
Input
Input
Input
Input
Mode
Op
Bi-dir
Bi-dir
Output
Op Mode
NC-SI Reference Clock Input
Synchronous clock reference for receive, transmit, and control
interface. This signal is a 50 MHz clock +/- 50 ppm.
Note: If not used, should have an external pull-down resistor.
Also, this clock is in addition to and separate from the XTAL
clock.
NC-SI Carrier Sense/Receive Data Valid (CRS/DV).
NC-SI Receive Data 0
Data signals to the Manageability Controller (MC).
NC-SI Receive Data 1
Data signals to the MC.
NC-SI Transmit Enable
Note: If not used, should have an external pull-down resistor.
NC-SI Transmit Data 0
Data signals from the MC
Note: If not used, should have an external pull-up resistor.
NC-SI Transmit Data 1
Data signal from the MC
Note: If not used, should have an external pull-up resistor.
Enables Test Mode
Test pins are overloaded on the functional signals as described
in the pin description text of this section. The pin is active
high.
Note: This pin should be externally pulled down for normal
operation.
SMBus Data
Stable during the high period of the clock (unless it
is a start or stop condition).
SMBus Clock
One clock pulse is generated for each data bit
transferred.
SMBus Alert
Acts as an interrupt pin of a slave device on the
SMBus in pass-through mode.
Name and Function
Name and Function
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