KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 11

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.1
Intel
®
Table 2-1. Main Channel Interface Signals
E8870DH DDR Memory Hub (DMH) Datasheet
The following notations are used to describe the signal types and their drive state:
Main Channel Interface
The Main Channel is the interface between the SNC and DMH.
•
•
•
•
•
•
•
I
O
I/O Bidirectional input/output pin
Z
L
H
?
DQA[8:0]
DQB[8:0]
RQ[7:0]
Signal
CTMN
CMD
CTM
SCK
SIO
Input pin
Output pin
Tri-stated
Driven low
Driven high
Output state is indeterminate
CMOS
CMOS
CMOS
Type
1.8V
1.8V
1.8V
RSL
RSL
RSL
RSL
RSL
I/O
I/O
I/O
I
I
I
I
I
State during
Deassertion
PWRGOOD
?
?
I
I
I
I
I
I
Data Bus, Data Byte A:
Bidirectional 9-bit data bus A. These correspond to the
DQA[8:0] signals on the RAC.
Data Bus, Data Byte B:
Bidirectional 9-bit data bus B. These correspond to the
DQB[8:0] signals on the RAC.
Request Control:
These signals carry the memory control packets (MCP)
from the SNC to the DMH. These correspond to the
RRq[2:0] and CRq[4:0] signals on the RAC.
Serial I/O Chain:
Serial input/output pins used for reading and writing
control registers.
Serial Clock:
Clock source used for timing of the SIO and CMD
signals. This corresponds to the SCK signal on the RAC.
Serial Command:
Serial command input used for control register read and
write operations. This corresponds to the CMD signal on
the RAC.
Clock to RAC Master:
One of the two differential transmit clock signals used for
DMH to RAC Master operations.
Clock to RAC Master Complement:
One of the two differential transmit clock signals used for
DMH to RAC Master operations.
Description
2
2-1