KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 12

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.2
2-2
Table 2-1. Main Channel Interface Signals (Continued)
Table 2-2. Branch Channel Interface Signals
Branch Channel Interface
The DMH drives two DDR Branch Channels. Channel 0 signals are prefixed with BC0 and channel 1
with BC1. Except for
the signal that applies to both ports. Unless specified in
electrically identical, meaning they use the same voltage and current levels.
BC0DQ[71:0]
BC1DQ[71:0]
BC0CS#[7:0]
BC1CS#[7:0]
BC0BA[1:0]
BC1BA[1:0]
BC0A[14:0]
BC1A[14:0]
BC0RAS#
BC1RAS#
BC0CAS#
BC1CAS#
BC0WE#
BC1WE#
BC0CKE
BC1CKE
Signal
CFMN
Signal
CFM
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
Class II
Class II
Class II
Class II
Class II
Class II
Class II
Class II
Table
Type
Type
RSL
RSL
I/O
O
O
O
O
O
O
O
I
I
2-2, the prefix is omitted in this document when discussing an aspect of
State during
State during
Deassertion
Deassertion
PWRGOOD
PWRGOOD
L
L
Z
L
L
L
L
L
I
I
Intel
Clock from RAC Master:
One of the differential receive clock signals used for RAC
Master to DMH operation.
Clock from RAC Master Complement:
One of the differential receive clock signals used for RAC
Master to DMH operation.
SDRAM Address:
Used for providing multiplexed row and column address
to SDRAM. Each set of address pins can drive up to eight
rows of SDRAM.
SDRAM Bank Active:
Used to select the bank within a device.
SDRAM Data:
BC0DQ and BC1DQ are independent to allow different
data to be read or written on both ports simultaneously.
SDRAM Row Address Strobe:
Used with CS#, CAS# and WE# to specify the SDRAM
command. Each signal can drive up to eight SDRAM
rows. CS# selects the row.
SDRAM Column Address Strobe:
Used with CS#, RAS# and WE# to specify the SDRAM
command. These signals are used to latch the column
and bank addresses. Each signal can drive up to eight
SDRAM rows.
SDRAM Write Enable:
Used with CS#, CAS# and RAS# to specify the SDRAM
command. These signals are used for write and
precharge operations of SDRAM. Each signal can drive
up to eight SDRAM rows.
SDRAM Chip Select:
These signals are used for selecting one of eight SDRAM
rows. CS#[0] is used to select the first row and CS#[1] is
used to select a second row if present, etc. to CS#[7]
which selects the last row.
SDRAM Clock Enable:
These signals are used for signaling commands to an
SDRAM row.
®
E8870DH DDR Memory Hub (DMH) Datasheet
Table
2-2, signals on BC0 and BC1 are
Description
Description