KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 20

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Registers
3.7
3-6
SDI – SDRAM Initialization Register
Address:
Default:
Access:
Size:
15:11
10
9:8
7
6
5:3
2.0
Bit
Reserved
Broadcast SIC (BRD):
When this bit is set to 1, the command specified by the SIC field (bits [2:0]) is issued to all SDRAM
rows on both branch channels. When this bit is 0, the SIC command is issued only to the branch
channel and row specified by the BC and CS fields.
Mode Register Function (MRF):
These bits define the value of BA[1:0] driven on the SDRAM pins during an MRS command. The
bits driven onto A[14:0] are defined in the preceding MRF register.
Initiate SIC Operation (ISO):
When set to 1, the execution of the command specified in the SIC field starts. After the execution is
complete, the DMH clears this bit to 0. The software must check to see if this bit is 0 before writing
to this register.
Branch Channel (BC):
Specifies the branch channel to be used with the SIC operation when the BRD field is set to 0.
1 = Branch Channel 1
1 = Branch Channel 0
DIMM Side Select (CS):
Specifies the DIMM Side (by Chip Select) to be used with the SIC operation when the BRD field is
set to 0.
Bits[5:3]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
SDRAM Initialization Command (SIC):
This field allows the DMH to issue various commands to the SDRAM row specified by the CS field,
on the branch channel specified by the BC field. This field is provided for BIOS to initialize the
SDRAMs. The BIOS programs this field with an appropriate command and then sets the ISO field
to logic one. When the DMH observes the ISO field set to 1 it performs the operation specified by
the SIC field. Upon completion of the operation, DMH sets the ISO field to logic 0.
Bits[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
07h
0000h
R/W
16 bits
DIMM Side Select
CS#[0]
CS#[1]
CS#[2]
CS#[3]
CS#[4]
CS#[5]
CS#[6]
CS#[7]
SIC
NOP Command: When DMH receives this command it issues a NOP command to the
DIMM side specified by the BC and CS bits of this register.
DDR delay line calibration: When DMH receives this command it issues a DDR delay
line calibration sequence to both branch channels. This command sets the DQS
strobe delay to 2.2ns. This command ignores CS, BC, and BRD.
Do not perform this command while in self-refresh mode.
Precharge: When DMH receives this command it issues a Precharge command to the
DIMM side specified by the BC and CS bits of this register. Precharge mode (all banks
or single bank) is determined by Bank Address (BA) and precharge all (PA) bits, which
are set through the MRF field of this register and the preceding MRF register. Refer to
Jedec Standard JESD79 for Precharge command details.
Mode Register Set: When DMH receives this command it issues a Mode Register Set
(MRS) command. The MRF bits of this register, combine with the preceding MRF
register to define the DDR SDRAM Mode register bits. Refer to Jedec Standard
JESD79 for Mode Register Set command details.
Intel
Description
®
E8870DH DDR Memory Hub (DMH) Datasheet