KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 5

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

6
7
Figures
Tables
Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
Ballout and Package Information ....................................................................................6-1
6.1
6.2
Testability ........................................................................................................................7-1
7.1
1-1
1-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
5-1
5-2
6-1
6-2
6-3
1-1
2-1
2-2
2-3
2-4
3-1
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-7
5-6
5-8
567-Ball OLGA1 Package Information ...............................................................6-1
Ballout Signal List...............................................................................................6-4
Parametric Test Mode ........................................................................................7-1
Fully Loaded SNC Example ...............................................................................1-1
DMH Driving Both DIMM Channels, Four DIMMs per Channel .........................1-2
DMH Block Diagram...........................................................................................4-2
Driving MCP to DIMM Address and Control Lines .............................................4-3
Phase Shifted MCP Command State Tracker and Correction ...........................4-4
Example of Valid Write Command Ordering ......................................................4-8
DRCG Connection Diagram .............................................................................4-10
Register Read MSIO Transaction ....................................................................4-10
Register Write MSIO Transaction.....................................................................4-11
MSIO Register Read Transaction ....................................................................4-12
MSIO Register Write Transaction.....................................................................4-12
Connection of DIMM Serial I/O Signals............................................................4-13
Random Byte Read Timing ..............................................................................4-14
Byte Write Register Timing...............................................................................4-15
PWRGOOD Sequence Method 1.....................................................................4-16
PWRGOOD Sequence Method 2.....................................................................4-17
SIO Reset Sequence........................................................................................4-17
SSTL-2 Common Clock AC Timing....................................................................5-5
SSTL-2 Source Synchronous AC Timing ...........................................................5-6
567-Ball (DMH) OLGA1 Package Dimensions – Top View................................6-1
567-Ball (DMH) OLGA1 Package Dimensions – Bottom View...........................6-2
567-Ball (DMH) OLGA1 Solder Balls Detail .......................................................6-3
Memory Size ......................................................................................................1-3
Main Channel Interface Signals .........................................................................2-1
Branch Channel Interface Signals......................................................................2-2
Reset and Miscellaneous Signals ......................................................................2-3
Voltage Reference Signals.................................................................................2-4
Unified Access Register Definitions .................................................................3-11
Encoding of ST and SF ......................................................................................4-3
Write Buffer Burst Operation for Read-Hit Operations .......................................4-9
MSIO Packet Field Definitions..........................................................................4-11
SCK Clock Divider Frequency Table................................................................4-14
DDR SDRAM Command Encoding for SDI Register .......................................4-16
Absolute Maximum Non-Operational DC Ratings at the Package Pin...............5-1
Voltage and Current Specifications ....................................................................5-1
DMH Main Channel Signal Groups ....................................................................5-2
Main Channel Vref Specification ........................................................................5-2
RSL Data Group, DC Parameters ......................................................................5-2
Main Channel “CMOS 1.8 I/O” DC Parameters .................................................5-3
RSL Clocks, DC Parameters..............................................................................5-3
DMH DDR Signal Groups...................................................................................5-3
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