KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 4

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5
iv
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
Electrical Specifications ..................................................................................................5-1
5.1
5.2
5.3
5.4
5.5
Branch Channel Periodic Calibration .................................................................4-6
4.5.1
4.5.2
Transfer Mode....................................................................................................4-6
4.6.1
4.6.2
Write Buffers ...................................................................................................... 4-7
Memory Translation Rules .................................................................................4-7
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
Error Mechanisms ..............................................................................................4-9
4.9.1
System Clocking ................................................................................................4-9
Serial Interface .................................................................................................4-10
4.11.1 Overview .............................................................................................4-10
4.11.2 MSIO Transaction Packet Formats .....................................................4-10
4.11.3 MSIO Bus Interface .............................................................................4-11
4.11.4 BSIO Bus Interface .............................................................................4-12
DDR SDRAM Transactions ..............................................................................4-15
4.12.1 DIMM Initialization ...............................................................................4-15
Reset................................................................................................................4-16
4.13.1 Power Good Sequence .......................................................................4-16
4.13.2 Hard Reset ..........................................................................................4-17
4.13.3 Local Reset .........................................................................................4-17
4.13.4 MSIO Local Reset ...............................................................................4-17
Initialization ......................................................................................................4-18
4.14.1 RAC Initialization .................................................................................4-18
4.14.2 DDR DIMM Sizing ...............................................................................4-18
4.14.3 DDR DIMM Initialization ......................................................................4-18
4.14.4 DDR Read Strobe Delay Calibration ...................................................4-19
4.14.5 DDR DIMM Path Delay Calibration .....................................................4-19
Non-Operational Maximum Rating .....................................................................5-1
Operation Power Delivery Specification.............................................................5-1
Main Channel Interface ......................................................................................5-2
5.3.1
5.3.2
5.3.3
DDR Interface ....................................................................................................5-3
5.4.1
5.4.2
5.4.3
5.4.4
Miscellaneous Signals Interface.........................................................................5-6
5.5.1
5.5.2
5.5.3
Slew Rate Calibration............................................................................4-6
Read Strobe 2.2 ns Delay Calibration ...................................................4-6
32-Byte Mode........................................................................................4-6
16-Byte Mode........................................................................................4-7
Read Rules ...........................................................................................4-7
Write Rules............................................................................................ 4-8
Miscellaneous Rules .............................................................................4-8
Read-Hit Handling .................................................................................4-8
Burst Operation .....................................................................................4-8
Invalid and Unsupported DIMM Transactions .......................................4-9
Support for Memory Device Failure.......................................................4-9
Main Channel Interface Reference Voltage Specification .....................5-2
DC Specifications.................................................................................. 5-2
AC Specifications .................................................................................. 5-3
Signal Group .........................................................................................5-3
DDR Reference Voltage Requirements ................................................5-4
DC Specifications.................................................................................. 5-4
AC Specifications .................................................................................. 5-4
Signal Groups .......................................................................................5-6
DC Characteristics ................................................................................5-6
AC Specification ....................................................................................5-7
Intel
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E8870DH DDR Memory Hub (DMH) Datasheet