KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 17

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.3
Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
MCTIM – Main Channel Timing Register
Address:
Default:
Access:
Size:
15:13
12
11
10:8
7:5
4:0
Bit
Reserved
Data Transfer Size (DTS):
1 = 16-byte Mode. The DMH transfers 16 bytes of data for each access.
0 = 32-byte Mode. The DMH transfers 32 bytes of data for each access.
Reserved
Main Channel Read Delay (t
Set by a SNC initialization procedure. Specifies the number of CTM pipe stages that data is
delayed from the time that it appears at the DQS I/O pins of the DMH to the time it is driven at the
DQA/DQB I/O pins of the DMH.
Bit[7:4]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Reserved
Main Channel Write Delay (t
Specifies additional pipestage delays from the completion of a MCP Write Command, to the
beginning of the write data transfer.
Bit[4:0]
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
03h
0006h
R/W
16 bits
2
3
4
5
6
7
8
9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
6
7
8
9
10
11
12
13
14
t
t
LVL
CWD
in CFMs
in CFMs
CWD
LVL
Bit[4:0]
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
):
):
Description
t
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CWD
in CFMs
Registers
3-3