KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 47

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.14.4
4.14.5
Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
DDR Read Strobe Delay Calibration
This procedure adjusts the DIMM read strobe delay to 2.2 ns as specified in Jedec Standard
JESD79.
Program the SDI register to perform a DDR Delay Line Calibration command by writing 81H to
the SDI register. Poll the SDI register until the ISO field is reset to 0 by the DMH. This calibrates
the strobes to be centered on data on DIMM read commands.
DDR DIMM Path Delay Calibration
Data (DQ) from memory is captured by the DMH using a source-synchronous clock (DQS)
supplied by the DIMMs. The JEDEC DDR DIMM standard requires DQS to be tristated while the
Branch Channel is in a quiescent state. This causes the DQ/DQS signals to float to the termination
voltage, and causes glitches on the DQ/DQS capture registers. Without special capture logic, these
glitches would leave the DMH in a non-functional state.
The DMH implements capture-window logic that turns on the DQ/DQS receivers only during the
data-phase of a Branch Channel Read transaction. While the capture-window is disabled, the DMH
ignores any events occurring on the DQ/DQS signals. In this way, the DMH isolates itself from
induced noise on the DQ/DQS lines during the quiescent intervals.
The capture-window occurs relative to the Read command, and during a time-interval that is a
function of DIMM Path Latency, DIMM CAS latency, and the DIMM registered delay. DIMM
CAS latency is obtained from the DIMM SPD ROM. A DIMM registered delay must always be
1 DIMM clock for the DMH.
For each DIMM side, BIOS must determine and program the t
Channel Timing
register values. The DMH provides an assist circuit to assist BIOS in ascertaining these values.
Register”) and t
DSDn
(Section 3.2, “DSTIM – DIMM Strobe Timing
DPL
(Section 3.4, “BCTIM – Branch
Functional Description
Register”)
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