KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 13

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

2.3
Intel
®
Table 2-2. Branch Channel Interface Signals (Continued)
Table 2-3. Reset and Miscellaneous Signals
E8870DH DDR Memory Hub (DMH) Datasheet
Reset and Test Signals
BC0SCLK#[3:0]
BC1SCLK#[3:0]
BC0DQS[17:0]
BC1DQS[17:0]
BC0SCLK[3:0]
BC1SCLK[3:0]
PWRGOOD
BC0SRCAL
BC1SRCAL
XOROUT
SREFFB
RESET#
XORIN
Signal
Signal
SREF
SDA
SCL
TSO
Open Drain
Open Drain
Open Drain
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
Class II
Class II
Class II
Class II
Class II
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
Type
2.5V
2.5V
2.5V
1.8V
1.8V
1.8V
1.8V
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
State during
State during
Deassertion
Deassertion
PWRGOOD
PWRGOOD
H
H
L
L
Z
L
Z
Z
Z
?
I
I
I
I
I
SDRAM Clocks:
One pair of differential clock signals for each DIMM.
SDRAM Data Strobe:
DDR data strobes. Some of these pins are dual mode,
and are DQM pins for X8 memory configuration as
specified in Jedec Standard JESD79.
SDRAM Feedback Output:
Used to calibrate the SDRAM clock.
SDRAM Feedback Input:
Used to calibrate the SDRAM clock.
Slew-rate Calibration:
BC0 tied to ground through 50 Ohm resistor
BC1 tied to VCC25 through 50 Ohm resistor
Serial Data/Address:
Used to read and write the Serial Presence Detect
EEPROMS associated with the DIMMs Controlled by this
DMH.
Serial Clock:
Used to read and write the Serial Presence Detect
EEPROMS associated with the DIMMs Controlled by this
DMH.
Disables all outputs except TSO and XOROUT.
Power Good:
This pin is used for asynchronous reset of the entire
DMH.
DMH Reset:
This signal is used for resetting the DMH internal logic
during power up sequence.
Parametric XOR tree input.
Parametric XOR tree output.
Description
Description
Signal Description
2-3