KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 32

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
4.2.4
4.2.5
4.3
4-4
Figure 4-3. Phase Shifted MCP Command State Tracker and Correction
MCP for DIMM Read/Write Command
A DIMM read/write command MCP is translated into a DDR DIMM read packet or DDR DIMM
write packet, as defined in Jedec Standard JESD79. Read/write MCPs are only valid as an MCP-B
packet.
Two categories of extended commands exist. A DIMM extended command is translated into a
DDR DIMM packet, as defined in Jedec Standard JESD79. A DMH extended command is used to
perform RAC calibration, and will not generate any externally observable cycles on a branch
channel.
DMH Time Synchronization Packet
The DMH maintains an internal MCP state tracker that must be synchronized to the SNC after
reset. The DMH state tracker could be phase shifted by 0 to 3 clocks relative to the SNC as shown
in
initialization (see
Packet to the DMH. This causes the DMH to stall its internal clock and MCP state tracker, bringing
them in sync.
MCP for Extended Commands
Figure 4-3
(depicted in this example shifted 2 clocks, or 4 clock edges). During the RAC
CFM
CFM
CFM
CFM
CFM
CFM
Section 4.14.1, “RAC
RQ
RQ
RQ
RQ
RQ
RQ
State:
State:
State:
State:
State:
State:
0
0
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
A
A
4
4 5 6 7 0
0
Packet
Sy nc
5 6 7 0 1 2 3
1 2 3 4 5 6 7
A
A
Packet
Sy nc
Initialization”), the SNC sends a Time Synchronization
B
B
0 0 0
B
B
Intel
®
0
4 5 6 7 0 1
0 1 2 3 4 5
E8870DH DDR Memory Hub (DMH) Datasheet
1 2 3 4 5
Before
SNC
Sends
Commands
Before
DMH
Misinterprets
State of
Sy nc Packet
SNC
Sends
Sy nc Packet
DMH
Adjusts to
Sy nc Packet
After
SNC
Sends
Commands
After
DMH
Correctly
Interprets State
of Sy nc Packet
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