KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 43

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.11.4.5
4.11.4.6
4.11.4.7
4.12
4.12.1
Intel
®
Figure 4-12. Byte Write Register Timing
E8870DH DDR Memory Hub (DMH) Datasheet
Upon receiving the MSIO SPDW command, the DMH generates the Byte Write Register I
command sequence on the BSIO interface as shown in
BSIO command has completed by setting the WOD bit of the DMH SPD register to 1 (see
Section 3.10, “SPD – Serial Presence Detect Status
Changing the Default SPD Device ID
In
reset, the default SPD device ID is 0AH (DIMM device type). The DMH provides a mechanism to
change the device ID.
To change the device ID, software programs the SPDID register with a new SPD device ID while
the BSIO interface is quiescent. Then, software performs one BSIO Read command to any SPD
address (it is not necessary for a device to respond to the address) to load the new device ID. This
first transaction will have an invalid Device ID, and its returned data and completion status must be
ignored. Afterwards, software may perform any supported BSIO commands, and the newly loaded
device ID will be used.
I
Refer to the I
I
I
If there is an error in the transaction such that the SPD EEPROM does not signal an acknowledge,
or holds SCK longer than the allowed time-out period of 25 ms, the transaction will time out. The
DMH will discard the cycle and set the BBE bit of the DMH SPD register to 1 to indicate this error
(see
DMH begins counting after the last bit of data is transferred to the DIMM and the DMH is waiting
for a response.
DDR SDRAM Transactions
DIMM Initialization
DIMM initialization is done by BIOS through the serial interface. The SDI register (see
Section 3.7, “SDI – SDRAM Initialization
used by BIOS to cause specific initialization sequences to be sent to the DIMMs over the DIMM
command lines.
commands available through the SDI register.
2
2
2
•
•
C protocols:
C Protocols
C Bus Timeout
Figure 4-11
Random Byte Read
Byte Write
Section 3.10, “SPD – Serial Presence Detect Status
S
S
P
D
3
S
P
D
2
Slave Address
2
C Bus Specification for standard timing protocols. The DMH supports the following
and
S
P
D
1
Table 4-5
S
P
D
0
Figure
C
2
C
1
4-12, the SPD device ID is represented by the SPD[3:0] bit fields. After
shows the SDRAM command encoding for the respective SDRAM
0
C
W
R
/
A
C
K
S
A
7
S
A
6
Byte Address
S
A
5
Register”), accessible through the MSIO interface, is
S
A
4
S
A
3
S
A
2
Register”).
S
A
1
Figure
Register”). The timeout counter within the
S
A
0
A
C
K
4-12. The DMH indicates that the
DATA
Functional Description
A
C
K
2
P
C
001191
4-15