KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 45

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.13.2
4.13.3
4.13.4
Intel
Figure 4-14. PWRGOOD Sequence Method 2
Figure 4-15. SIO Reset Sequence
®
E8870DH DDR Memory Hub (DMH) Datasheet
The second method
scenario, SCK must begin with a clean and complete cycle.
Hard Reset
Upon the deassertion of the RESET# signal, the DMH will asynchronously reset all internal logic
except for programmable registers, calibration registers, and the serial interface. Write buffers are
invalidated by hard reset. SNC guarantees that all memory pages have been closed and data flushed
prior to hard reset. The DMH requires a sufficient number of quiescent clock cycles on the Main
Channel to allow any pending memory commands to complete prior to hard reset.
Local Reset
The MSIO interface can be locally reset. MSIO reset will reset the MSIO and BSIO interfaces to an
initial state.
BIOS can reset the DMH through the MSIO serial interface by issuing an SIO reset sequence as
shown in
sequence on CMD resets the state machines controlling the MSIO pins. Programmable registers in
the DMH are not affected by this reset.
MSIO Local Reset
SCK
CMD
Figure
0
SCK
PWRGOOD
V
4-15. CMD is sampled on both the rising and falling edges of SCK. A 1-1-0-0
CC
(Figure
1
4-14) is used when SCK begins after PWRGOOD assertion. In this
2
3
4
Commands
Ready f or
T0
Serial
5
T1
Functional Description
6
7
001227
001193
4-17