KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 36

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
4.8.2
4.8.3
4.8.4
4.8.5
4-8
Figure 4-4. Example of Valid Write Command Ordering
The following write rules apply:
Write to Read turnaround time of the same memory address must be spaced a minimum of
16 CFMs apart to allow the data/address to be valid in the Write FIFO.
A read-hit occurs when a Read Command MCP matches a valid write buffer. The DMH will
provide the data for the read-hit from the write buffer, and will also generate the associated Branch
Channel Read Command. The stale data from the Read Command is thrown away. Allowing the
Branch Channel Read Command to occur prevents the DMH from masking the auto-precharge
function that may be set in the Read Command.
Burst Operation
The DMH supports a subset of available DDR DIMM burst operations.
SNC uses DMH read-hit logic and follow the rules:
Write Rules
Miscellaneous Rules
Read-Hit Handling
1. Open-Page write policy is not supported.
2. An Activate for Write command must be issued to open a page before a write to the page is
3. Neither an Activate for Write nor a Write can be issued to a page that is currently open due to
4. Strict ordering of Write Command MCPs must be maintained relative to their respective
1. Writes must always be of natural alignment.
2. Read alignments shown in
3. The DMH Write buffer provides the burst operation support on a read-hit as defined in
ACT-W1
allowed.
an Activate for Read.
Activate for Write commands.
Table
y
y
Two Outstanding
Act Commands
All Activ ate f or Write Commands precede their respectiv e Write Command MCPs.
Strong ordering between Activ ate and Write Commands are maintained.
4-2.
ACT-W 2
Wr 1
Table 4-2
ACT-W 3
are the only alignments supported.
Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
Wr 2
Wr 3
ACT-W 4
Wr 4
001182a