KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 46

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
4.14
4.14.1
4.14.2
4.14.3
4-18
Initialization
After the Power Good sequence
is in the powered-down idle state, i.e. the serial interface is active, while the rest of the DMH is
held in reset. Branch Channel clocks are stopped and Branch Channel Clock Enables are
deasserted. All Main Channel I/Os are indeterminate and may be driving the bus until the RAC
reset sequence is completed.
The DMH core is programmatically sequenced out of reset and initialized by BIOS. Before BIOS
begins the process of initializing the DMH, all DMH inputs must be stable and the Main Channel
and MSIO clocks must be running.
DMH behaves deterministically at the end of the reset and initialization sequence.
RAC Initialization
RAC initialization is performed by BIOS after power up of the DMH. This involves using the
MSIO serial interface to send a sequence of RAC initialization steps to the DMH to power up the
DMH’s core. BIOS completes RAC initialization by synchronizing the SNC and DMH main
channels.
Upon completion of the RAC initialization procedure, the DMH is in the powered up idle state, i.e.
the DMH provides stable DIMM clocks and drives a NOP command state on each branch channel,
DIMM Clock Enable (CKE) on each branch channel is asserted, and the DMH main channel will
be synchronized and ready to accept commands.
DDR DIMM Sizing
DIMM Sizing is performed by using the BSIO interface to interrogate the DIMM SPD logic to
determine DIMM population and characteristics.
DDR DIMM Initialization
Branch channel initialization must be performed after power-up and RAC initialization of the
DMH. BIOS will use the MSIO bus (see
Branch Channel initialization steps to the DMH.
1. Size the DMH for DIMMs by using the MSIO SPDR command (see
1. For each DIMM, issue SDI register commands (see
2. Program the DIMM MRS registers for correct CAS latency and burst size using the SDI Mode
Transaction Packet
read-only registers, and processing the information (See
Interface”).
Register”) for precharge, mode register set, and auto refresh, as necessary to perform the
manufacturer’s DIMM power-up sequence (see Jedec Standard JESD79 and also
manufacturers requirements for specific DIMMs).
Register Set command (see
corresponding DIMM CAS latency field of the BCTIM register (see
Branch Channel Timing
of the MCTIM register
to match the SNC burst size. Also program the DGR register
Geometry
through SPD.
Register”) with the geometry of the DIMMs as determined by sizing the DIMMs
Formats”) to generate BSIO transactions, reading all SPD EEPROM
(Section 3.3, “MCTIM – Main Channel Timing
Register”) to match the DIMM CAS latency. Program the DTS field
Section 3.7, “SDI – SDRAM Initialization
(Section 4.13.1, “Power Good Sequence”)
Section 4.11, “Serial
Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
Section 3.7, “SDI – SDRAM Initialization
Section 4.11.4, “BSIO Bus
Interface”) to send a sequence of
(Section 3.5, “DGR – DIMM
Section 4.11.2, “MSIO
Section 3.4, “BCTIM –
Register”). Program the
has occurred, the DMH
Register”) burst side