KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 25

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.15
3.15.1
Intel
®
Table 3-1. Unified Access Register Definitions
E8870DH DDR Memory Hub (DMH) Datasheet
MUARD – DMH Unified Access Register Data
DMH Unified Access Registers
The DMH provides the MUARS and MUARD registers, which allow access to information in the
high-speed core. These registers are read and written through the MSIO serial interface (see
Section 4.11, “Serial
To read or write information to the high-speed core through this interface, first write the MUARS
register SELECT field with the entry to be accessed. Then, to write data to the entry selected, write
the data to the MUARD register. Or to read data from the entry selected, read the MUARD
register. Some entries are read-only as indicated in
Address:
Default:
Access:
Size:
15:0
The following selectors control attributes for Branch Channel 0 (BC0) and Branch Channel 1 (BC1) data path.
BC0: 0H
BC1: 20H
BC0: 1H
BC1: 21H
BC0: 2H
BC1: 22H
BC0: 3H
BC1: 23H
p-type: 4H
n-type: 24H
p-type: 5H
n-type: 25H
BC0: 6H
BC1: 26H
BC0: 7H
BC1: 27H
BC0: 8H
BC1: 28H
MUARS
Bit
Select
Data. Refer to
1Bh
0000h
R/W
16 bits
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
Interface”).
Bit[5] - Reserved.
Bit[4] - Latch Delay Value
Bits[3:0] - Iterations per short
calibration
Bits[5:0] - Encoded Delay
Bits[5:0] - Encoded Delay
Bits[5:0] - Encoded Delay
Bit[15] - Manual Calibration Start
Bit[14] - Range Error
Bit[13] - Reserved
Bit[12] - Auto Calibration Enable
Bit[11] - Reserved
Bit[10] - Disable Zero Calibration
Bit[9:8] - Hysteresis Control
Bit[7:4] - Reserved
Bit[3:0] - Scale Factor
Bits[7:0]
Entire Register
Entire Register
Entire Register
Table 3-1 “Unified Access Register Definitions.”
MUARD
Description
Table
3-1.
Strobe delay calibration control.
Bottom chunk strobe delay.
Middle chunk strobe delay.
Top chunk strobe delay.
Slew-rate calibration control register.
Process counter for slew-rate calibration.
Clock driver calibration LUT entry 0.
Clock driver calibration LUT entry 1.
Clock driver calibration LUT entry 2.
Description
Registers
3-11