KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 18

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Registers
3.4
3-4
BCTIM – Branch Channel Timing Register
Address:
Default:
Access:
Size:
15:9
8
7
6:4
3
2:0
Bit
Reserved
Manual DIMM Path Latency Calibration Enable (DPLE):
Setting this bit to 1 causes the DMH to perform a DIMM Path Latency calibration on both branch
channels. Upon completion of the calibration, the DMH resets the bit to 0. The Main channel should
remain quiescent throughout the calibration procedure. The results of this command are stored in
the t
Reserved
Branch Channel DIMM Path Latency (t
Specifies the number of CFM round-trip delays from the time a DIMM drives data to the time it
appears at the I/O pins of the DMH. This field is typically set by the DIMM path calibration
procedure (see DPLE field above), but can be set manually as well.
Bit[6:4]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Reserved
DIMM CAS Latency (t
This bit specifies the number of SCLKs from when a read command is sampled by the SDRAMs to
when the DMH samples read data from the SDRAMs.
Bit[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
04h
0002h
R/W
16 bits
DPL
field of this register.
0
1
2
3
4
5
6
7
Reserved
Reserved
2
Reserved
Reserved
1.5
2.5
Reserved
t
t
DPL
CL
in SCLKs
in CFMs
CL
):
DPL
Intel
):
Description
®
E8870DH DDR Memory Hub (DMH) Datasheet