KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 15

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Registers
3.1
3.2
Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
The DMH has internal configuration and control registers. These registers are accessed via the
MSIO bus (see
Gen – General Purpose Register
DSTIM – DIMM Strobe Timing Register
Offsets each DIMM read-strobe-capture-window forward, relative to the base setting contained in
the t
Address:
Default:
Access:
Size:
15:0
Address:
Default:
Access:
Size:
15:14
13:12
11:10
Bit
Bit
DPL
field.
General purpose R/W register.
Branch Channel 1, DIMM 7 Strobe Offset (t
Bits [15:14] t
0 0
0 1
1 0
1 1
Branch Channel 1, DIMM 6 Strobe Offset (t
Bits [13:12] t
0 0
0 1
1 0
1 1
Branch Channel 1, DIMM 5 Strobe Offset (t
Bits [11:10] t
0 0
0 1
1 0
1 1
01h
0000h
R/W
16 bits
02h
0000h
R/W
16 bits
Section 4.11, “Serial
0
1
2
3
0
1
2
3
0
1
2
3
DSD7
DSD6
DSD5
in CFMs
in CFMs
in CFMs
Interface”).
Description
Description
DSD7
DSD6
DSD5
):
):
):
3
3-1