KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 22

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Registers
3.10
3-8
This register provides an interface between the MSIO bus (SCK, SIO, CMD) and BSIO bus
(SCL,SDA) that is used to access the Serial Presence Detect EEPROM. See
Bus Interface.”
SPD – Serial Presence Detect Status Register
2:0
(cont’d)
Address:
Default:
Access:
Size:
15
14
13
12
11:8
7:0
Bit
Bit
RAC Initialization Command (RIC):
This field allows the BIOS to initialize DMH RAC. The BIOS programs this field with an appropriate
command and sets the IRO field to logic one. The DMH then performs the operation specified by
the RIC field. Upon successful completion of the operation, the DMH sets the IRO field to logic
zero. For procedures, see
Bits[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Read Data Valid (RDO):
This bit is set by the DMH when the Data field of this register receives read data from the SPD
EEPROM. It is cleared by the DMH when an MSIO SPDR command is received.
Write Operation Done (WOD):
This bit is set by the DMH when the SPDW command has been completed on the BSIO bus. It is
cleared by the DMH when an MSIO SPDW command is received.
BSIO Bus Error (BBE):
This bit is set by the DMH if it initiates a BSIO bus transaction that does not complete successfully.
It is cleared by the DMH when an MSIO SPDR or SPDW command is received.
Busy state (BUSY):
This bit is set by the DMH while an SPD command is executing.
Clock Divider (DIV):
Sets the BSIO clock frequency from 100 KHz to 4 KHz. Refer to
Data:
Holds data read from SPDR commands. Refer to
Random Read.”
0Fh
00FFh
R/W: DIV
R-O: RDO, WOD, BBE, BUSY, DATA
16 bits
Description
RAC Power Up Sequence: DMH performs the internal RAC and 200 MHz logic power
up sequence. Required to power up and reset the RAC.
RAC Initialization: When the DMH receives this command, it internally performs an
Auto-Current and Temperature Calibration of the DMH RAC. Upon completion of the
calibration procedures, the DMH sets the RSP bit, indicating that a Clock-Sync packet
must now be sent to the DMH. After clock synchronization, the DMH sets the RC bit to
logic one and resets the IRO bit to logic zero to indicate successful completion of the
procedure. This operation must be performed exactly one time after the RAC Power
Up Sequence is performed.
RAC Manual-Current Calibration: When DMH receives this command it issues a
Manual-Current Calibration sequence to the RAC, and loads the value contained in
the RCC.
RAC Temperature Calibration: When DMH receives this command it issues a
Temperature Calibration sequence to the RAC.
Reserved
Reserved
Reserved
Reserved
Section 4.14.1, “RAC Initialization.”
Intel
Description
Description
®
E8870DH DDR Memory Hub (DMH) Datasheet
Section 4.11.4.3, “BSIO Request Packet for SPD
Section 4.11.4.2, “Clock Divider.”
Section 4.11.4, “BSIO