KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 7

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Overview
1.1
Intel
®
Figure 1-1. Fully Loaded SNC Example
E8870DH DDR Memory Hub (DMH) Datasheet
System Architecture
The DDR Memory Hub (DMH) is a memory translator hub that provides a mechanism for
tunneling DDR SDRAM transactions between a Main Channel (RAMBUS* interface) and two
Branch Channels (DDR SDRAM interfaces). While all RAMBUS signals maintain electrical
compatibility with RDRAM pins, the RAMBUS signals are logically redefined to packetize DDR
SDRAM I/O traffic. The DMH tunnels SDRAM packets between the Main Channel and a Branch
Channel with deterministic timing.
The DMH interfaces two 8-byte-wide DDR DIMM channels to a single, 2-byte-wide Main
Channel as shown in
DMH supports a maximum of 8 DIMMs (4 each on each branch channel), and requires at least 1
DIMM.
SNC
Figure
1-2. Each DDR DIMM channel may contain from 0 to 4 DIMMs. The
Main Channel
Main Channel
Main Channel
Main Channel
DMH
DMH
DMH
DMH
Branch Channel 0
Branch Channel 0
Branch Channel 1
Branch Channel 0
Branch Channel 1
Branch Channel 0
Branch Channel 1
Branch Channel 1
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
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