KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 75

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Testability
7.1
Intel
®
Table 7-1. Parametric Test Control Signals
Table 7-2. Parametric Test Pin Order
E8870DH DDR Memory Hub (DMH) Datasheet
There is no JTAG circuitry in the DMH. To check the connectivity of the pins, the DMH supports
the use of the parametric XOR tree test mode.
parametric test.
Parametric Test Mode
A single XOR chain is provided in the DMH. The TSO signal needs to be asserted (active high)
during XOR chain mode. The pin orders are shown in
Tristate Outputs
Parametric Data In
Parametric Data Out
Pin Order
Function
10
12
13
14
15
16
17
18
19
20
21
22
23
11
1
2
3
4
5
6
7
8
9
TSO
XORIN
XOROUT
Pin Names
DQA[8]
DQA[7]
DQA[6]
DQA[5]
DQA[4]
DQA[3]
DQA[2]
DQA[1]
DQA[0]
DQB[0]
XORIN
CTMN
CFMN
RQ[7]
RQ[6]
RQ[5]
RQ[4]
RQ[3]
RQ[2]
RQ[1]
RQ[0]
CTM
CFM
Signal
Table 7-1
I/O
O
I
I
Pin Order
Table
Tristate all outputs except XOROUT.
Input pin to the Parametric Tree.
Output pin from the Parametric Tree.
lists the signals needed for enabling the
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
7-2.
Description
Reserved (Ball Number: V10)
Reserved (Ball Number: U9)
BC0DQS[16]
PWRGOOD
Pin Names
BC0DQ[56]
BC0DQ[60]
BC0DQ[63]
BC0DQ[61]
BC0DQS[7]
RESET#
DQB[1]
DQB[2]
DQB[3]
DQB[4]
DQB[5]
DQB[6]
DQB[7]
DQB[8]
CMD
SCK
SDA
SCL
SIO
7
7-1