KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 29

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
4.1
Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
Operation Overview
The DMH receives commands from the SNC through the Main Channel or Main Channel Serial
I/O (MSIO) bus interface. These commands are encoded as Memory Control Packets (MCPs; refer
to
When the DMH receives an MCP, it decodes it and performs an operation. If the MCP contains a
DIMM command, the DMH performs a serial-to-parallel conversion of the command contained in
the MCP packet, and drives the command to the specified DIMM. For a read command, the DMH
captures the data from the DIMM, performs a parallel-to-serial conversion, and then returns the
data to the SNC, and pushing the data onto the top of a write FIFO. Simultaneously, the DMH then
pops a write from the bottom of the write FIFO and commits it to the appropriate DIMM. The
DMH controls data timing for registered DIMMs and CAS latency.
The DMH requires periodic calibration of its RAC and DDR I/Os. DIMMs also require periodic
refresh cycles. The DMH provides no autonomous periodic functions. It is the responsibility of the
SNC to maintain all periodic timers, and send the appropriate calibration MCPs to the DMH.
The DMH does not generate or detect data parity or ECC. However, the DMH does provide a
generic 72-bit wide DDR DIMM data path. The SNC can be designed to generate and detect parity
or ECC with the additional 8 bits, beyond the 64 data bits.
The DMH contains registers for configuration and control. These registers are accessed through the
MSIO bus, a three-signal CMOS interface.
The DMH contains an I
via the MSIO bus, and is functional immediately after reset deassertion. This interface conforms to
the I
Figure 4-1
Description”
Section 4.2, “Main Channel to Branch Channel
2
C specification for a single-master with multiple-slave devices.
is a block diagram of internal logic blocks in the DMH. Refer to
for pin descriptions.
2
C interface that is intended for sizing DIMMs. This interface is controlled
Translation”) and sent across the Main Channel.
Chapter 2, “Signal
4
4-1