KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 34

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
4.5
4.5.1
4.5.2
4.6
4.6.1
4-6
Branch Channel Periodic Calibration
Like the Main Channel, the Branch Channels must also be periodically calibrated to prevent timing
violations that could occur as a result of variations in voltage and temperature over time. Since the
minimum required frequency of periodic Branch Channel calibration events falls below the
frequency for periodic calibration of the Main Channel, all periodic Branch Channel calibration
events are embedded within the periodic Main Channel calibration events discussed in the previous
section.
Slew rate calibration compensates for variations in process, voltage, and temperature. The DMH
provides two slew-rate calibration procedures. An extensive initialization procedure for long slew
rate calibration is done once after reset. The periodic slew rate calibration is embedded within the
RAC short temperature calibration event. When the DMH receives a Short Temperature Calibrate
MCP (see
performs a single short slew rate calibration procedure.
As defined in Jedec Standard JESD79, the memory controller is responsible for internally delaying
the data strobes (DQS) during the data phase of a DDR read transaction to center them on the data.
The DMH provides two strobe delay calibration procedures.
The long strobe delay calibration procedure is done once after reset (see
Read Strobe Delay
delay circuits, which takes approximately 1 s.
The periodic delay line calibration is embedded within the periodic RAC short current calibration
event. When the DMH receives a Short Current Calibrate MCP (see
Extended Commands”)
its RAC, and the Branch Channel Read Data 2.2 ns DQS Delay Calibration
Transfer Mode
Two parameters must be programmed to set the DMH transfer mode. The DDR DIMM burst length
in each DIMM’s MRS register is programmed via the DMH DDR SDRAM initialization register
(Section 3.7, “SDI – SDRAM Initialization
programming the DMH data transfer size (DTS) in the Main Channel Timing register
“MCTIM – Main Channel Timing
must match.
32-Byte Mode
In this mode, each DDR SDRAM is programmed to use a burst length of 32 bytes (four transfers)
across the Branch Channel. The Mode Register of each SDRAM must be programmed for a burst
length of 4, and for sequential mode (as defined in the Jedec Standard JESD79). In addition, the
DMH MCTIM register DTS field must be set to a 32-byte mode. The DMH sends and receives
data across the Main Channel in bursts of 16 transfers at 2 bytes/transfer.
Slew Rate Calibration
Read Strobe 2.2 ns Delay Calibration
Section 4.2.5, “MCP for Extended
Calibration”). This procedure performs a complete initialization of the strobe
from the Main Channel, the DMH initiates the current calibrate process of
Register”). DIMM burst length and Main Channel burst length
Register”). The Main Channel burst length is set by
Commands”) from the Main Channel, the DMH
Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
Section 4.2.5, “MCP for
Section 4.14.4, “DDR
(Section 3.3,