KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 31

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.2.1
4.2.2
4.2.3
Intel
®
Figure 4-2. Driving MCP to DIMM Address and Control Lines
Table 4-1. Encoding of ST and SF
E8870DH DDR Memory Hub (DMH) Datasheet
MCP Format and Timing
A Memory Control Packet (MCP) is generated by the SNC, and is sent over the Request Control
bus (RQ[7:0]) to the DMH. An MCP is a 32-bit packet sent over two CFMs (Main Channel
clocks), at double data rate as depicted in
An MCP that begins in state 0 (MCP CMD-A) will appear on the DDR DIMM address and control
lines 2.5 CFMs later. An MCP that begins in state 4 (MCP CMD-B) will appear on the DDR
DIMM address and control lines 4.5 CFMs later. An MCP that begins in state 1, 2, 3, 5, 6 or 7 is
illegal and will have undetermined effects.
No external MCP tracking signal is provided by the SNC. The DMH internally maintains an MCP
state tracker that must be synchronized with the SNC. Upon reset deassertion, the DMH MCP state
tracker is arbitrarily set. Before the SNC can send any MCP packets, it must first synchronize the
DMH state tracker. Refer to
MCP Command Type Field
There are two bits (ST and SF) in the MCP which indicate the packet type. The encoding of ST and
SF is shown in
MCP for DIMM Activate Command
A DIMM Activate Command MCP is translated into a DDR DIMM Activate packet, as defined in
Jedec Standard JESD79.
CMD_A is an internally generated and tracked state in DMH. There is no externally observable version of this signal.
CFM
CMD_A
RQ
State:
By te #:
ST
0
0
1
1
Table
0 1 2 3 4 5 6 7
0 1 2 3 0 1 2 3
A
4-1.
Section 4.3, “DMH Time Synchronization Packet”
B
SF
0
1
0
1
Figure
4-2. The MCP may begin in state 0 or in state 4.
Read/Write Command (CMD-B only)
Extended Command
Activate Command
Operation
No Packet
Functional Description
for the details.
001224a
4-3