KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 39

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.11.3
Intel
®
Figure 4-7. Register Write MSIO Transaction
Table 4-3. MSIO Packet Field Definitions
E8870DH DDR Memory Hub (DMH) Datasheet
The following sections detail the available packet formats and the operations that can be performed
on the serial control bus.
MSIO Bus Interface
The MSIO bus is a three-pin low-speed CMOS serial interface. SCK and CMD are input-only, and
SIO is bi-directional.
SCK is driven by the SNC at up to 1 MHz.
CMD is driven by the SNC, and is used to indicate the beginning of a new command, or a reset
sequence. CMD is sampled on both edges of SCK by the DMH.
SOP[3:0]
C[2:0]
SA[11:0]
SD[15:0]
Field
Serial Op-code (SOP). Specifies the MSIO operation to perform.
0000 - SRD: Serial read of the DMH register specified in SA[11:0].
0001 - SWR: Serial write of the DMH register specified in SA[11:0].
1101 - SPDW: SPD Write Byte to SPD EEPROM. The EEPROM device is specified by C[2:0],
SA[7:0], and SD[7:0] of the Write MSIO transaction. Bits C[2:0] specifies the DIMM SPD
EEPROM address, SA[7:0] contains the byte address, and SD[7:0] contains data to be written to
the SPD EEPROM. When the write has completed, the WOD bit of the SPD register is set to 1 by
the DMH (see
1110 - SPDR: SPD Random Read the SPD EEPROM. The EEPROM device is specified by
C[2:0], SA[7:0] of the Read MSIO transaction. Bits C[2:0] specifies the DIMM SPD EEPROM
address, SA[7:0] contains the byte address. The data read from the EEPROM is placed in the
data field of the SPD register. The RDO bit of the SPD register (see
Presence Detect Status
All other combinations are reserved.
Figure 4-12
Serial Register Address. For SRD and SWR commands, SA[11:0] selects which control register
is read or written. For SPDW and SPDR commands, SA[7:0] selects which DIMM register is read
or written.
Serial Data. For SRD and SWR commands, the 16-bits of data read from or written to the
selected control register in the DMH. For SPDW command, SD[7:0] is the data written to the
DIMM register.
Specifies the DIMM serial address for SPDW and SPDR commands. See
SINT
SCK
SRQ
SA
SD
for placement in I
Section 3.10, “SPD – Serial Presence Detect Status
0
Reserved
1
Reserved
2
Register”) indicates when the data is available.
3
2
C packets.
4
5
6
SOP[3:0]
SD[15:0]
Description
7
0
8
SA[11:0]
9
10
Reserved
11
12
Register”).
13
Section 3.10, “SPD – Serial
Functional Description
C[2:0]
14
Figure 4-11
15
and
001186
4-11