MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 116

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

ColdFire Flash Module (CFM)
6.3
Figure 6-2
space of the MCU. The starting address of the array is determined by the CFM array base address which
must reside on a natural size boundary; that is, the CFM array base address must be an integer multiple of
the array size. The CFM register space must reside on a 64 byte boundary as determined by the CFM
register base address.
form a contiguous non-volatile memory space. Each pair of 32-bit blocks (even and odd) interleave every
4 bytes to form a 256-Kbyte section of memory.
The CFM module has hardware interlocks to protect data from accidental corruption. The <<BLOCK
NAME>> memory array is logically divided into 16-Kbyte sectors for the purpose of data protection and
access control. A flexible scheme allows the protection of any combination of logical sectors (see
Section 6.3.4.4, “CFM Protection Register
supervisor/user and program/data space access to these sectors.
6-4
Configuration Field
1
(0x0000_0400–
0x0000_0417)
The MCF5281 and MCF5214 support only Logical Block 0.
0x0007 FFFF
0x0004 000C
0x0003 FFFF
0x0000 000C
0x0004 0008
0x0004 0004
0x0004 0000
0x0000 0008
0x0000 0004
0x0000 0000
Memory Map
shows the memory map for the CFM array. The CFM array can reside anywhere in the memory
The CFM on the MCF5281 and MCF5214 is constructed with four banks of
32K x 16-bit Flash arrays to generate 256 Kbytes of 32-bit Flash memory.
3H[1]
2H[1]
3H[0]
2H[0]
1H[1]
0H[1]
1H[1]
0H[0]
Figure 6-2
shows how multiple 32,768 by 16-bit Flash physical blocks interleave to
3L[1]
2L[1]
3L[0]
2L[0]
1L[1]
0L[1]
1L[1]
0L[0]
Figure 6-2. CFM Array Memory Map
(CFMPROT)”). A similar mechanism is available to control
NOTE
Flash Physical Block 2
Flash Physical Block 0
Array 2H
Array 0H
Memory
Memory
2H[31]
0H[31]
2H[0]
0H[0]
Each physical block = 128 Kbytes
Logical Block 1 (256 Kbytes)
Logical Block 0 (256 Kbytes)
Array 2L
Array 0L
Memory
Memory
2L[31]
0L[31]
2L[0]
0L[0]
Each memory array = 64 Kbytes
Flash Physical Block 3
Flash Physical Block 1
Array 3H
Array 1H
Memory
Memory
3H[31]
1H[31]
3H[0]
1H[0]
(32 bits wide × 32K)
Array 3L
Array 1L
Memory
Memory
3L[31]
1L[31]
(16 bits wide × 32K)
3L[0]
1L[0]
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