MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 279

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
10–8
5–4
2–0
Bit
7
6
3
Name
IMRS Initiate mode register set (
CBM Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and
PS
—
IP
—
bank select lines to correspond to different addresses, these resources are programmable. CBM
determines the addresses onto which these functions are multiplexed.
Note: It is important to set CBM according to the location of the command bit.
This encoding and the address multiplexing scheme handle common SDRAM organizations. Bank
select bits include a base bit and all address bits above for SDRAMs with multiple bank select bits.
Reserved, should be cleared.
SDRAMs. In initialization, IMRS should be set only after all DRAM controller registers are initialized
and
block programs the SDRAM’s mode register. Thus, the address of the access should be programmed
to place the correct mode information on the SDRAM address pins. Because the SDRAM does not
register this information, it doesn’t matter if the IMRS access is a read or a write or what, if any, data is
put onto the data bus. The DRAM controller clears IMRS after the
0 Take no action
1 Initiate
Port size. Indicates the port size of the associated block of SDRAM, which allows for dynamic sizing of
associated SDRAM accesses. PS functions the same in asynchronous operation.
00 32-bit port
01 8-bit port
1x 16-bit port
Initiate precharge all (
finished. Accesses via IP should be no wider than the port size programmed in PS.
0 Take no action.
1 A
Reserved, should be cleared.
executed after all DRAM controller registers are programmed. After IP is set, the next write to an
appropriate SDRAM address generates the
PALL
PALL
and
command is sent to the associated SDRAM block. During initialization, this command is
MRS
Table 15-5. DACRn Field Descriptions (continued)
REFRESH
command
PALL
commands have been issued. After IMRS is set, the next access to an SDRAM
MRS
) command. The DRAM controller clears IP after the
CBM
000
001
010
011
100
101
110
111
) command. Setting IMRS generates a
Command Bit
Description
PALL
17
18
19
20
21
22
23
24
command to the SDRAM block.
Bank Select Bits
18 and up
19 and up
20 and up
21 and up
22 and up
23 and up
24 and up
25 and up
MRS
Synchronous DRAM Controller Module
MRS
command finishes.
command to the associated
PALL
command is
15-7