MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 227

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

The timing relationship of chip selects (CS[7:0]), byte selects (BS[3:0]), and output enable (OE) with
respect to CLKOUT is similar in that all transitions occur during the low phase of CLKOUT. However,
due to differences in on-chip signal routing, signals may not assert simultaneously.
13.4.1
When a bus cycle is initiated, the device first compares the address of that bus cycle with the base address
and mask configurations programmed for chip selects 0–7 (configured in CSCR0–CSCR7) and DRAM
block 0 and 1 address and control registers (configured in DACR0 and DACR1). If the driven address
compares with one of the programmed chip selects or DRAM blocks, the appropriate chip select is asserted
or the DRAM block is selected using the specifications programmed by the user in the respective
configuration register. Otherwise, the following occurs:
Table 13-2
Freescale Semiconductor
•
•
•
If the address and attributes do not match in CSCR or DACR, the processor runs an external
burst-inhibited bus cycle with a default of external termination on a 32-bit port.
Should an address and attribute match in multiple CSCRs, the matching chip-select signals are
driven; however, the processor runs an external burst-inhibited bus cycle with external termination
on a 32-bit port.
Should an address and attribute match both DACRs or a DACR and a CSCR, the operation is
undefined.
Bus Cycle Execution
shows the type of access as a function of match in the CSCRs and DACRs.
CLKOUT
CS[7:0]
BS[3:0]
Figure 13-2. Connections for External Memory Port Sizes
OE
Figure 13-3. Chip-Select Module Output Timing Diagram
Byte Enable
32-Bit Port
16-Bit Port
Processor
8-Bit Port
Data Bus
External
Memory
Memory
Memory
D[31:24]
Byte 0
Byte 0
Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
BS3
D[23:16]
Byte 1
Byte 1
Byte 3
BS2
indeterminate values
Driven with
indeterminate values
D[15:8]
Byte 2
BS1
Driven with
Byte 3
D[7:0]
BS0
External Interface Module (EIM)
13-3