MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 93

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

The following pseudocode explains basic MAC or MSAC instruction functionality. This example is
presented as a case statement covering the three basic operating modes with signed integers, unsigned
integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {},
indicates a concatenation operation.
switch (MACSR[6:5])
{
Freescale Semiconductor
case 0:
•
if (MACSR.OMC == 0 || MACSR.PAVn == 0)
The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1
indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is
added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the
EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because
a product can overflow, the following guidelines are implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right shifts.
— For signed, word operations, the sign bit is shifted into the product on right shifts unless the
— For all left shifts, a zero is inserted into the lsb position.
if ((product[63:39] != 0x0000_00_0) and and
then {
product is zero. For signed, longword operations, the sign bit is shifted into the product unless
an overflow occurs or the product is zero, in which case a zero is shifted in.
MACSR.PAVn = 0
/* select the input operands */
if (sz == word)
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
then {if (U/Ly == 1)
}
else {operandY[31:0] = Ry[31:0]
}
then {
}
then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]}
then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}
/* MACSR[S/U, F/I] */
/* signed integers */
else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]}
if (U/Lx == 1)
else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]}
operandX[31:0] = Rx[31:0]
MACSR.PAVn = 1
MACSR.V = 1
if (inst == MSAC and and
then if (product[63] == 1)
else if (MACSR.OMC == 1)
/* product overflow */
then result[47:0] = 0x0000_7fff_ffff
else result[47:0] = 0xffff_8000_0000
then /* overflowed MAC,
if (product[63] == 1)
then result[47:0] = 0xffff_8000_0000
else result[47:0] = 0x0000_7fff_ffff
saturationMode enabled */
MACSR.OMC == 1)
(product[63:39] != 0xffff_ff_1))
Enhanced Multiply-Accumulate Unit (EMAC)
3-15