MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 502

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

General Purpose I/O Module
1. Although ports NQ, QA, QB, TA, and TB are not part of the ports module, they are included here for comprehensiveness.
26-2
DDATA[3:0] / PDD[7:4]
SIZ1 / PE3 / SYNCA
SIZ0 / PE2 / SYNCB
PST[3:0] / PDD[3:0]
A[23:21] / PF[7:5] /
TIP / PE0 / SYNCB
TS / PE1 / SYNCA
D[23:16] / PB[7:0]
D[31:24] / PA[7:0]
A[20:16] / PF[4:0]
BS[3:0] / PJ[7:4]
A[15:8] / PG[7:0]
D[15:8] / PC[7:0]
CS[3:0] / PJ[3:0]
D[7:0] / PD[7:0]
A[7:0] / PH[7:0]
CS[6:4]
PEL[3]
PEL[2]
PEL[1]
PEL[0]
Figure 26-1. MCF5214 and MCF5216 Ports Module Block Diagram
PORT DD
PORT EL
PORT C
PORT D
PORT G
PORT H
PORT A
PORT B
PORT E
PORT F
PORT J
CANRX / PAS3 / URXD2
CANTX / PAS2 / UTXD2
OE / PE7
TA / PE6
TEA / PE5
R/W / PE4
PEL[7]
PEL[6]
PEL[5]
PEL[4]
SDRAM_CS[1:0] /
PAS5 / URXD2
PAS4 / UTXD2
PSD[2:1]
PORT NQ
PORT QB
PORT TA
PORT TB
PORT QA
PORT AS
PORT QS
PORT SD
PORT TC
PORT TD
PORT UA
1
1
1
1
1
SDA / PAS1 / URXD2
SCL / PAS0 / UTXD2
IRQ[7:1] / PNQ[7:1]
AN56 / PQA4 / ETRIG2
AN55 / PQA3 / ETRIG1
AN53 / PQA1 / MA1
AN52 / PQA0 / MA0
AN3 / PQB3 / ANZ
AN2 / PQB2 / ANY
AN1 / PQB1 / ANX
AN0 / PQB0 / ANW
QSPI_CS[3:0] / PQS[6:3]
QSPI_CLK / PQS2
QSPI_DIN / PQS1
QSPI_DOUT / PQS0
SRAS / PSD5
SCAS / PSD4
DRAMW / PSD3
SCKE / PSD0
GPTA[3:0] / PTA[3:0]
GPTB[3:0] / PTB[3:0]
DTIN3 / PTC[3] / URTS1 / URTS0
DTOUT3 / PTC[2] / URTS1 / URTS0
DTIN2 / PTC[1] / UCTS1 / UCTS0
DTOUT2 / PTC[0] / UCTS1 / UCTS0
DTIN1 / PTD[3] / URTS1 / URTS0
DTOUT1 / PTD[2] / URTS1 / URTS0
DTIN0 / PTD[1] / UCTS1 / UCTS0
DTOUT0 / PTD[0] / UCTS1 / UCTS0
URXD1 / PUA[3]
UTXD1 / PUA[2]
URXD0 / PUA[1]
UTXD0 / PUA[0]
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