MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 305

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
27–25
24–23
21–20
18–17
Bits
22
19
16
START Start transfer.
SSIZE Source size. Determines the data size of the source bus cycle for the DMA control module.
DSIZE Destination size. Determines the data size of the destination bus cycle for the DMA controller.
Name
BWC
SINC
DINC
—
Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a
multiple of the BWC value, the DMA releases the bus. For example, if BCR24BIT is 0, BWC is 001
(512 bytes or value of 0x0200), and BCR is 0x1000, the bus is relinquished after BCR values of
0x0E00, 0x0C00, 0x0A00, 0x0800, 0x0600, 0x0400, and 0x0200. If BCR24BIT is 0, BWC is 110, and
BCR is 33000, the bus is released after 232 bytes because the BCR is at 32768, a multiple of 16384.
Reserved, should be cleared.
Source increment. Controls whether a source address increments after each successful transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
Destination increment. Controls whether a destination address increments after each successful
transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
0 DMA inactive
1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared
automatically after one system clock and is always read as logic 0.
Table 16-3. DCRn Field Descriptions (continued)
Encoding
000
001
010
011
100
101
110
111
DMA has priority and does not negate its
request until transfer completes.
BCR24BIT = 0
Description
16384
32768
1024
2048
4096
8192
512
BCR24BIT = 1
1048576
131072
262144
524288
16384
32768
65536
DMA Controller Module
16-9