MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 145
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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7.3.2.12 Interrupt Controllers (INTC0, INTC1)
The interrupt controller is not affected by any of the low-power modes. All logic between the input sources
and generating the interrupt to the processor will be combinational to allow the ability to wake up the CPU
processor during low-power stop mode when all system clocks are stopped.
An interrupt request will cause the CPU to exit a low-power mode only if that interrupt’s priority level is
at or above the level programmed in the interrupt priority mask field of the CPU’s status register (SR). The
interrupt must also be enabled in the interrupt controller’s interrupt mask register as well as at the module
from which the interrupt request would originate.
7.3.2.13 Fast Ethernet Controller (FEC)
In wait and doze modes, the FEC may generate an interrupt to exit the low-power modes.
In stop mode, the FEC stops immediately and freezes operation, register values, state machines, and
external pins. During this mode, the FEC clocks are shut down. Coming out of stop mode returns the FEC
to operation from the state prior to the low-power mode entry.
The MCF5214 and MCF5216 do not contain an FEC.
7.3.2.14 I/O Ports
The I/O ports are unaffected by entry into a low-power mode. These pins may impact low-power current
draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is
exited by a reset, the state of the I/O pins will revert to their default direction settings.
7.3.2.15 Reset Controller
A power-on reset (POR) will always cause a chip reset and exit from any low-power mode.
In wait and doze modes, asserting the external RSTI pin for at least four clocks will cause an external reset
that will reset the chip and exit any low-power modes.
In stop mode, the RSTI pin synchronization is disabled and asserting the external RSTI pin will
asynchronously generate an internal reset and exit any low-power modes. Registers will lose current
values and must be reconfigured from reset state if needed.
If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE, LOLRE) bits
in the synthesizer control register are set, then any loss-of-clock or loss-of-lock will reset the chip and exit
any low-power modes.
If the watchdog timer is still enabled during wait or doze modes, then a watchdog timer timeout may
generate a reset to exit these low-power modes.
When the CPU is inactive, a software reset cannot be generated to exit any low-power mode.
7.3.2.16 Chip Configuration Module
The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode is
exited by a reset, chip configuration may be executed if configured to do so.
Freescale Semiconductor
•
•
Clearing the ECNTRL[ETHER_EN] bit disables the FEC function.
The FEC is unaffected by wait mode and may generate an interrupt to exit this mode.
Power Management
7-9
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