MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 276

MCF5282CVM66

Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet

Specifications of MCF5282CVM66

Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5282CVM66
Manufacturer:
FREESCAL
Quantity:
152
Part Number:
MCF5282CVM66
Manufacturer:
FREESCALE
Quantity:
1 002
Part Number:
MCF5282CVM66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5282CVM66
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
MCF5282CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Synchronous DRAM Controller Module
15.2.1
Table 15-2
15.2.2
The DRAM controller registers memory map is shown in
15.2.2.1 DRAM Control Register (DCR)
The DCR, shown in
15-4
SRAS
SCAS
DRAMW
SDRAM_CS[1:0
]
SCKE
BS[3:0]
IPSBAR
Signal
Offset
0x04C
0x040
0x044
0x048
0x050
0x054
DRAM Controller Signals
describes the behavior of DRAM signals in synchronous mode.
Memory Map for SDRAMC Registers
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by
the SDRAM. SRAS should be connected to the corresponding SDRAM SRAS.
Synchronous column address strobe. Indicates a valid column address is present and can be latched by
the SDRAM. SCAS should be connected to the corresponding SDRAM SCAS.
DRAM read/write. Asserted for write operations and negated for read operations.
Row address strobe. Select each memory block of SDRAMs connected to the processor. One
SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals.
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs.
Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down
mode in which operations are suspended or capable of entering self-refresh mode. SCKE functionality is
controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SCKE to provide
command-bit functionality.
Column address strobe. BS[3:0] function as byte enables to the SDRAMs. They connect to the BS signals
(or mask qualifiers) of the SDRAMs.
DRAM control register (DCR) [p. 15-4]
Figure
[31:24]
Table 15-2. Synchronous DRAM Signal Connections
15-2, controls refresh logic.
Table 15-3. DRAM Controller Registers
DRAM address and control register 0 (DACR0) [p. 15-6]
DRAM address and control register 1 (DACR1) [p. 15-6]
DRAM mask register block 0 (DMR0) [p. 15-8]
DRAM mask register block 1 (DMR1) [p. 15-8]
[23:16]
Description
Table
15-3.
[15:8]
Freescale Semiconductor
[7:0]

Related parts for MCF5282CVM66