MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 384

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

General Purpose Timer Modules (GPTA and GPTB)
20.5.17 Pulse Accumulator Counter Register (GPTPACNT)
20.5.18 GPT Port Data Register (GPTPORT)
20-16
Bit(s)
Bit(s)
15–0
7–4
3–0
Address
Reset
Field
R/W
Address
Reset
Field
R/W
PORTT
PACNT
15
Name
Name
—
Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT)
7
Figure 20-20. GPT Port Data Register (GPTPORT)
Contains the number of active input edges on the PAI pin since the last reset.
Note: Reading the pulse accumulator counter registers immediately after an active
edge on the PAI pin may miss the last count since the input first has to be synchronized
with the bus clock.
To ensure coherent reading of the PA counter, such that the counter does not
increment between back-to-back 8-bit reads, it is recommended that only word (16-bit)
accesses be used. These bits are read anytime, write anytime.
Reserved, should be cleared.
GPT port input capture/output compare data. Data written to GPTPORT is buffered
and drives the pins only when they are configured as general-purpose outputs.
Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1)
reads the latched value. Writing to a pin configured as a GPT output does not change
the pin state. These bits are read anytime (read pin state when corresponding
PORTTn bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write
anytime.
Table 20-21. GPTPORT Field Descriptions
Table 20-20. GPTPACR Field Descriptions
6
—
IPSBAR + 0x1A_001A, 0x1B_001B
IPSBAR + 0x1A_001D, 0x1B_001D
5
0000_0000_0000_0000
0000_0000
4
PACNT
R/W
R/W
Description
3
Description
PORTT
Freescale Semiconductor
0
0