MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 456

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

I
24.1.2
I
minimizing the interconnection between devices. This bus is suitable for applications that require
occasional communication between many devices over a short distance. The flexible I
additional devices to connect to the bus for expansion and system development.
The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of
operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus
loading. The maximum communication length and the number of devices connected are limited by a
maximum bus capacitance of 400 pF.
The I
corruption in the event that multiple devices attempt to control the bus simultaneously. This feature
supports complex applications with multiprocessor control and can be used for rapid testing and alignment
of end products through external connections to an assembly-line computer.
24.1.3
The I
24-2
2
2
C Interface
C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
•
•
•
•
•
•
•
•
•
•
•
2
2
C system is a true multiple-master bus; it uses arbitration and collision detection to prevent data
C module has these key features:
Compatibility with I
Multiple-master operation
Software-programmable for one of 50 different serial clock frequencies
Software-selectable acknowledge bit
Interrupt-driven, byte-by-byte data transfer
Arbitration-lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
Overview
Features
The I
information on system configuration, protocol, and restrictions, see The I
Bus Specification, Version 2.1.
The GPIO module must be configured to enable the peripheral function of
the appropriate pins (refer to
prior to configuring the I
2
C module is compatible with the Philips I
2
C bus standard version 2.1
2
C module.
Chapter 26, “General Purpose I/O
NOTE
NOTE
2
C bus protocol. For
Module”)
Freescale Semiconductor
2
2
C bus allows
C