MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 669

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

31.4.2.3 Bypass Register
The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS instruction is
selected.
31.4.2.4 JTAG_CFM_CLKDIV Register
The JTAG_CFM_CLKDIV register is a 7-bit clock divider for the CFM that is used with the
LOCKOUT_RECOVERY instruction. It controls the period of the clock used for timed events in the CFM
erase algorithm. The JTAG_CFM_CLKDIV register must be loaded before the lockout sequence can
begin.
31.4.2.5 TEST_CTRL Register
The TEST_CTRL register is a 3-bit shift register path from TDI to TDO when the
ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold
register on the rising edge of TCLK when the TAP state machine is in the update-DR state.
31.4.2.6 Boundary Scan Register
The boundary scan register is connected between TDI and TDO when the EXTEST or
SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins,
and selects a logic value and direction for bidirectional pins or high impedance for tri-stated pins.
The boundary scan register contains bits for bonded-out and non bonded-out signals excluding JTAG
signals, analog signals, power supplies, compliance enable pins, and clock signals.
31.5
31.5.1
The JTAG module consists of a TAP controller state machine, which is responsible for generating all
control signals that execute the JTAG instructions and read/write data registers.
Freescale Semiconductor
31–28
27–22
21–12
11–1
Bits
0
Functional Description
JTAG Module
JEDEC Joint electron device engineering council ID bits. Indicate the reduced JEDEC ID for Freescale.
Name
PRN
PIN
DC
ID
Part revision number. Indicate the revision number of the project.
Design center.
Part identification number. Indicate the device number.
IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the
bypass register according to the IEEE standard 1149.1.
Table 31-4. IDCODE Register Field Descriptions
Description
IEEE 1149.1 Test Access Port (JTAG)
31-5