MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 184

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Clock Module
The lock detect function uses two counters. One is clocked by the reference and the other is clocked by the
PLL feedback. When the reference counter has counted N cycles, its count is compared to that of the
feedback counter. If the feedback counter has also counted N cycles, the process is repeated for N + K
counts. Then, if the two counters still match, the lock criteria is relaxed by 1/2 and the system is notified
that the PLL has achieved frequency lock.
After lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using
the alternate count and compare process. If the counters do not match at any comparison time, then the
LOCK flag is cleared to indicate that the PLL has lost lock. At this point, the lock criteria is tightened and
the lock detect process is repeated.
The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL tries to
lock. Alternating between tight and relaxed lock criteria prevents the lock detect function from randomly
toggling between locked and non-locked status due to phase sensitivities.
for detecting locked and non-locked conditions.
In external clock mode, the PLL is disabled and cannot lock.
9.7.4.6
Once the PLL acquires lock after reset, the LOCK and LOCKS flags are set. If the MFD is changed, or if
an unexpected loss of lock condition occurs, the LOCK and LOCKS flags are negated. While the PLL is
in the non-locked condition, the system clocks continue to be sourced from the PLL as the PLL attempts
to relock. Consequently, during the relocking process, the system clocks frequency is not well defined and
may exceed the maximum system frequency, violating the system clock timing specifications.
However, once the PLL has relocked, the LOCK flag is set. The LOCKS flag remains cleared if the loss
of lock is unexpected. The LOCKS flag is set when the loss of lock is caused by changing MFD. If the
PLL is intentionally disabled during stop mode, then after exit from stop mode, the LOCKS flag reflects
the value prior to entering stop mode once lock is regained.
9-14
PLL Loss of Lock Conditions
with Tight Lock
Criteria
Start
Number of Feedback
Reference Cycles
Cycles Elapsed
and Compare
Count N
Figure 9-6. Lock Detect Sequence
≠
Reference Count
Feedback Count
In Same Count/Compare Sequence
Feedback Count = N
Condition and Notify
Reference Count =
Set Relaxed Lock
and Notify System of Loss
System of Lock
Lock Detected.
Loss of Lock Detected
Set Tight Lock Criteria
Condition
of Lock Condition
Reference Count =
Feedback Count = N + K
IN Same Count/Compare Sequence
Figure 9-6
Reference Count
≠
Feedback Count
and Compare Number
of Feedback Cycles
Reference Cycles
Count N + K
Elapsed
Freescale Semiconductor
shows the sequence