MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 592

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Queued Analog-to-Digital Converter (QADC)
To prepare the QADC for a scan sequence, write to the CCW table to specify the desired channel
conversions. The criteria for queue execution is established by selecting the queue operating mode. The
queue operating mode determines what type of trigger event starts queue execution. A trigger event refers
to any of the ways that cause the QADC to begin executing the CCWs in a queue or subqueue. An external
trigger is only one of the possible trigger events.
A scan sequence may be initiated by:
The queue can be scanned in single pass or continuous fashion. When a single-scan mode is selected, the
scan must be engaged by setting the single-scan enable bit. When a continuous-scan mode is selected, the
queue remains active in the selected queue operating mode after the QADC completes each queue scan
sequence.
During queue execution, the QADC reads each CCW from the active queue and executes conversions in
three stages:
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A software command
Expiration of the periodic/interval timer
An external trigger signal
An external gated signal (queue 1 only)
Initial sample
Final sample
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P — Pause after Conversion
BYP — Bypass Buffer Amplifier
IST — Input Sample Time
CHAN — Channel Number and
Conversion Command
Beginning of Queue 1
Beginning of Queue 2
P
9
Word (CCW) Table
End of Queue 1
End of Queue 2
10-bit Conversion Command
until Next Trigger
BYP
8
Figure 28-43. QADC Conversion Queue Operation
End-of-Queue Code
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Word Format
[7:6]
IST
CHAN
[5:0]
Channel Select,
A/D Conversion
Sample, Hold,
15 14 13 12 11 10
S
0
0 0 0 0 0
Right-Justified, Unsigned Result
Left-Justified, Unsigned Result
Left-Justified, Signed Result
RESULT
10-bit Result, Readable in
[15:6]
RESULT
[15:6]
Three 16-BIT Formats
Result Word Table
0
0
RESULT
0 0 0 0 0
0 0 0 0 0
[9:0]
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[5:0]
[5:0]
Freescale Semiconductor
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