MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 275

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

15.2
By running synchronously with the system clock, SDRAM can (after an initial latency period) be accessed
on every clock; 5-1-1-1 is a typical burst rate to the SDRAM. Unlike the MCF5272, this processor does
not have an independent SDRAM clock signal. For this processor, the timing of the SDRAM controller is
controlled by the CLKOUT signal.
Note that because the processor cannot have more than one page open at a time, it does not support
interleaving.
SDRAM controllers are more sophisticated than asynchronous DRAM controllers. Not only must they
manage addresses and data, but they must send special commands for such functions as precharge, read,
write, burst, auto-refresh, and various combinations of these functions.
commands.
SDRAMs operate differently than asynchronous DRAMs, particularly in the use of data pipelines and
commands to initiate special actions. Commands are issued to memory using specific encodings on
address and control pins. Soon after system reset, a command must be sent to the SDRAM mode register
to configure SDRAM operating parameters.
Freescale Semiconductor
Command
WRITE
SELFX
READ
ACTV
PALL
SELF
MRS
NOP
REF
SDRAM Controller Operation
Activate. Executed before
Mode register set.
No-op. Does not affect SDRAM state machine; DRAM controller control signals negated;
SDRAM_CS[1:0] asserted.
Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is
opened.
Read access. SDRAM registers column address and decodes that a read access is occurring.
Refresh. Refreshes internal bank rows of an SDRAM component.
Self refresh. Refreshes internal bank rows of an SDRAM component when it is in low-power mode.
Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared.
Write access. SDRAM registers column address and decodes that a write access is occurring.
READ
Table 15-1. SDRAM Commands
or
WRITE
executes; SDRAM registers and decodes row address.
Definition
Table 15-1
Synchronous DRAM Controller Module
lists common SDRAM
15-3