MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 153

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 8
System Control Module (SCM)
This section details the functionality of the System Control Module (SCM) which provides the
programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit core
watchdog timer (CWT), and the system control registers and logic. Specifically, the system control
includes the internal peripheral system (IPS) base address register (IPSBAR), the processor’s dual-port
RAM base address register (RAMBAR), and system control registers that include the core watchdog timer
control.
8.1
The SCM provides the control and status for a variety of functions including base addressing and address
space masking for both the IPS peripherals and resources (IPSBAR) and the ColdFire core memory spaces
(RAMBAR). The CPU core supports two memory banks, one for the internal SRAM and the other for the
internal Flash.
The SACU provides the mechanism needed to implement secure bus transactions to the system address
space.
The programming model for the system bus arbitration resides in the SCM. The SCM sources the
necessary control signals to the arbiter for bus master management.
The CWT provides a means of preventing system lockup due to uncontrolled software loops via a special
software service sequence. If periodic software servicing action does not occur, the CWT times out with a
programmed response (interrupt) to allow recovery or corrective action to be taken.
8.2
The SCM includes these distinctive features:
Freescale Semiconductor
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IPS base address register (IPSBAR)
— Base address location for 1-Gbyte peripheral space
— User control bits
Processor-local memory base address register (RAMBAR)
System control registers
— Core reset status register (CRSR) indicates type of last reset
— Core watchdog control register (CWCR) for watchdog timer control
— Core watchdog service register (CWSR) to service watchdog timer
System bus master arbitration programming model (MPARK)
System access control unit (SACU) programming model
— Master privilege register (MPR)
— Peripheral access control registers (PACRs)
— Grouped peripheral access control registers (GPACR0, GPACR1)
Overview
Features
8-1