MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 339

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

17.5.1.3
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs.
The Ethernet controller confirms transmission by clearing the ready bit (TxBD[R]) when DMA of the
buffer is complete. In the TxBD, the user initializes the R, W, L, and TC bits and the length (in bytes) in
the first longword and the buffer pointer in the second longword.
The FEC clears the R bit when the buffer is transferred. Status bits for the buffer/frame are not included in
the transmit buffer descriptors. Transmit frame status is indicated via individual interrupt bits (error
conditions) and in statistic counters in the MIB block. See
Map,”
Freescale Semiconductor
1
Offset + 0
Offset + 0
Offset + 6
0ffset + 4
The receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. The
buffer must reside in memory external to the FEC. The Ethernet controller never modifies this value.
Word
Word
Offset + 0
Offset + 2
Offset + 4
Offset + 6
for more details.
A[31:16]
Ethernet Transmit Buffer Descriptor (TxBD)
Field
A[15:0]
15
TO1
R
15
14
Field
15–0
15–0
When the software driver sets an E bit in one or more receive descriptors,
the driver should follow with a write to RDAR.
R
TO1
Table 17-29. Receive Buffer Descriptor Field Definitions (continued)
14
Ready. Written by the FEC and you.
0 The data buffer associated with this BD is not ready for transmission. You are free to manipulate
1 The data buffer, prepared for transmission by you, has not been transmitted or currently transmits.
Transmit software ownership. This field is reserved for software use. This read/write bit is not modified
by hardware nor does its value affect hardware.
RX data buffer pointer, bits [31:16]
RX data buffer pointer, bits [15:0]
this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted
or after an error condition is encountered.
You may write no fields of this BD after this bit is set.
Table 17-30. Transmit Buffer Descriptor Field Definitions
13
W
Figure 17-26. Transmit Buffer Descriptor (TxBD)
TO2
12
11
L
TC
10
Tx Data Buffer Pointer - A[31:16]
Tx Data Buffer Pointer - A[15:0]
ABC
9
NOTE
1
Data Length
—
8
Section 17.4.1, “MIB Block Counters Memory
Description
Description
—
7
—
6
—
5
—
4
Fast Ethernet Controller (FEC)
—
3
—
2
—
1
—
0
17-29