MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 466

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

I
24.3.8
The clock synchronization mechanism can acts as a handshake in data transfers. Slave devices can hold
I2C_SCL low after completing one byte transfer. In such a case, the clock mechanism halts the bus clock
and forces the master clock into wait states until the slave releases I2C_SCL.
Slaves may also slow down the transfer bit rate. After the master has driven I2C_SCL low, the slave can
drive I2C_SCL low for the required period and then release it. If the slave I2C_SCL low period is longer
than the master I2C_SCL low period, the resulting I2C_SCL bus signal low period is stretched.
24.4
The following examples show programming for initialization, signaling START, post-transfer software
response, signaling STOP, and generating a repeated START.
24.4.1
Before the interface can transfer serial data, registers must be initialized:
24.4.2
After completion of the initialization procedure, serial data can be transmitted by selecting the master
transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine whether the
serial bus is free. If the bus is free (IBB is cleared), the START signal and the first byte (the slave address)
can be sent. The data written to the data register comprises the address of the desired slave and the lsb
indicates the transfer direction.
The free time between a STOP and the next START condition is built into the hardware that generates the
START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, the
24-12
2
C Interface
1. Set I2FDR[IC] to obtain I2C_SCL frequency from the system bus clock. See
2. Update the I2ADR to define its slave address.
3. Set I2CR[IEN] to enable the I
4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and
Frequency Divider Register (I2FDR).”
interrupt-enable or not.
Initialization/Application Information
Handshaking and Clock Stretching
Initialization Sequence
Generation of START
If I2SR[IBB] is set when the I
following pseudocode sequence before proceeding with normal
initialization code. This issues a STOP command to the slave device,
placing it in idle state as if it were power-cycled on.
I2CR = 0x0
I2CR = 0xA0
dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
I2CR = 0x80
2
C bus interface system.
; re-enable
2
C bus module is enabled, execute the
NOTE
Freescale Semiconductor
Section 24.2.2, “I
2
C