MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 430

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

UART Modules
Table 23-7
Operating
23-10
MISC
Field
6–4
7
IPSBAR
Offset:
Reset:
Reserved, must be cleared.
MISC Field (this field selects a single command)
W
R
Modes,” show how these commands are used.
describes UCRn fields and commands. Examples in
0x00_0208 (UCR0)
0x00_0248 (UCR1)
0x00_0288 (UCR2)
000
001
010
011
100
101
110
111
0
0
7
NO COMMAND
RESET MODE
REGISTER POINTER
RESET RECEIVER
RESET
TRANSMITTER
RESET ERROR
STATUS
RESET BREAK
CHANGE INTERRUPT
START BREAK
STOP BREAK
Command
0
6
Figure 23-7. UART Command Registers (UCRn)
–
Table 23-7. UCRn Field Descriptions
—
Causes the mode register pointer to point to UMR1n.
Immediately disables the receiver, clears USRn[FFULL,RXRDY], and reinitializes
the receiver FIFO pointer. No other registers are altered. Because it places the
receiver in a known state, use this command instead of
reconfiguring the receiver.
Immediately disables the transmitter and clears USRn[TXEMP,TXRDY]. No other
registers are altered. Because it places the transmitter in a known state, use this
command instead of
Clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after
a data block is received.
Clears the delta break bit, UISRn[DB].
Forces UTXDn low. If the transmitter is empty, break may be delayed up to one bit
time. If the transmitter is active, break starts when character transmission
completes. Break is delayed until any character in the transmitter shift register is
sent. Any character in the transmitter holding register is sent after the break.
Transmitter must be enabled for the command to be accepted. This command
ignores the state of UCTSn.
Causes UTXDn to go high (mark) within two bit times. Any characters in the
transmit buffer are sent.
MISC
0
5
0
4
Description
TRANSMITTER DISABLE
0
3
Section 23.4.2, “Transmitter and Receiver
Description
TC
when reconfiguring the transmitter.
0
2
RECEIVER DISABLE
Access: User write-only
Freescale Semiconductor
1
0
RC
0
when
0