MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 379

MCF5282CVM66

Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet

Specifications of MCF5282CVM66

Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5282CVM66
Manufacturer:
FREESCAL
Quantity:
152
Part Number:
MCF5282CVM66
Manufacturer:
FREESCALE
Quantity:
1 002
Part Number:
MCF5282CVM66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5282CVM66
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
MCF5282CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
20.5.11 GPT System Control Register 2 (GPTSCR2)
Freescale Semiconductor
Bit(s)
Bit(s)
7–4
3–0
7
6
5
4
3
Address
Reset
Field
R/W
Name
Name
PUPT
RDPT
TCRE
TOI
CnI
Figure 20-13. GPT System Control Register 2 (GPTSCR2)
TOI
7
Reserved, should be cleared.
Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate
interrupt requests for each channel. These bits are read anytime, write anytime.
1 Corresponding channel interrupt requests enabled
0 Corresponding channel interrupt requests disabled
Enables timer overflow interrupt requests.
1 Overflow interrupt requests enabled
0 Overflow interrupt requests disabled
Reserved, should be cleared.
Enables pull-up resistors on the GPT ports when the ports are configured as inputs.
1 Pull-up resistors enabled
0 Pull-up resistors disabled
GPT drive reduction. Reduces the output driver size.
1 Output drive reduction enabled
0 Output drive reduction disabled
Enables a counter reset after a channel 3 compare.
1 Counter reset enabled
0 Counter reset disabled
Note: When the GPT channel 3 registers contain 0x0000 and TCRE is set, the GPT
counter registers remain at 0x0000 all the time. When the GPT channel 3 registers
contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter
registers go from 0xFFFF to 0x0000.
Table 20-14. GPTSCR2 Field Descriptions
Table 20-13. GPTIE Field Descriptions
6
IPSBAR + 0x1A_000D, 0x1B_000D
PUPT
5
RDPT
0000_0000
4
R/W
TCRE
Description
3
Description
General Purpose Timer Modules (GPTA and GPTB)
2
PR
0
20-11

Related parts for MCF5282CVM66