MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 637

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Table 30-15
30.5.2.2 Transmit Packet Format
The basic transmit packet,
Table 30-16
30.5.3
Table 30-17
each command. Issuing a BDM command when the processor is accessing debug module registers using
the WDEBUG instruction causes undefined behavior.
Freescale Semiconductor
.
15–0
Bits
15–0
Bits
16
16
S
16
16
C
Name
Name
15
BDM Command Set
15
S
D
C
D
describes receive BDM packet fields.
describes transmit BDM packet fields.
summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of
Control. This bit is reserved. Command and data transfers initiated by the development system should
clear C.
Data bits 15–0. Contains the data to be sent from the development system to the debug module.
Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be
ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a
new serial transfer after 32 processor clock periods.
S DataMessage
0 xxxxValid data transfer
0 0xFFFFStatus OK
1 0x0000Not ready with response; come again
1 0x0001Error—Terminated bus cycle; data invalid
1 0xFFFFIllegal command
Data. Contains the message to be sent from the debug module to the development system. The
response message is always a single word, with the data field encoded as shown above.
Figure
Table 30-16. Transmit BDM Packet Field Description
Table 30-15. Receive BDM Packet Field Description
30-14, consists of 16 data bits and 1 control bit.
Figure 30-14. Transmit BDM Packet
Figure 30-13. Receive BDM Packet
Data Field [15:0]
Description
Description
D
Debug Support
0
0
30-19