Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 100

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
As an example of how the codes are interpreted, consider
the case of eight bits per character and a residue code of
101. The number of valid bits for the previous, second
previous, and third previous bytes are 0, 7, and 8,
A frame is terminated by the detection of a closing flag.
Upon detection of the flag the following actions take place:
the contents of the Receive Shift Register are transferred
to the receive data FIFO; the Residue Code is latched, the
CRC Error bit is latched; the End of Frame upon reaching
the top of the FIFO can cause a special receive condition.
The processor then reads RR1 to determine the result of
the CRC calculation and the Residue Code.
Only the CRC-CCITT polynomial is used for CRC calcula-
tions in SDLC mode, although the generator and checker
can be preset to all 1s or all 0s. The CRC-CCITT polyno-
mial is selected by setting bit D2 of WR5 to 0. Bit D7 of
WR10 controls the preset value. If this bit is set to 1, the
generator and checker are preset to 1s, and if this bit is re-
set, the generator and checker are preset to all 0s.
The receiver expects the CRC to be inverted before trans-
mission, so it checks the CRC result against the value
0001110100001111. The SCC presets the CRC checker
whenever the receiver is in Hunt mode or whenever a flag
is received, so a CRC reset command is not necessary.
However, the CRC checker can be preset by issuing the
Reset CRC Checker command in WR0.
The CRC checker is automatically enabled for all data be-
tween the opening and closing flags by the SCC in SDLC
mode, and the Rx CRC Enable bit (D3) in WR3 is ignored.
The result of the CRC calculation for the entire frame is
valid in RR1 only when accompanied by the End of Frame
bit set in RR1. At all other times, the CRC Error bit in RR1
should be ignored by the processor.
On the NMOS/CMOS version, care must be exercised
so that the processor does not attempt to use the CRC
bytes that are transferred as data, because not all of the
bits are transferred properly. The last two bits of CRC
Third Previous
Byte
Figure 4-14. Residue Code 101 Interpretation
Second Previous
7-Bits
I - Field
Byte
respectively. This indicates that the information field (I-
field) boundary falls on the second previous byte as shown
in Figure 4-14.
are never transferred to the receive data FIFO and are
not recoverable.
On the ESCC, an enhancement has been made allowing
the 2nd byte of the CRC to be received completely. This
feature is useful when the application requires the 2nd
CRC byte as data. For example, applications which oper-
ate in transparent mode or protocols using the error check-
ing mechanism other than CRC-CCITT (like 32-bit CRC).
Note the following about SCC CRC operation:
A frame is terminated by a closing flag. When the SCC rec-
ognizes this flag:
The End of Frame bit, upon reaching the exit location of
the FIFO, will cause a special receive condition. The pro-
cessor may then read RR1 to determine the result of the
CRC calculation as well as the Residue Code. If either
the Rx Interrupt on Special Condition Only or the Rx In-
terrupt on First Character or Special Condition modes are
The normal CRC checking mechanism involves
checking over data and CRC characters. If the division
remainder is 0, there is no CRC error.
SDLC is different. The CRC generator, when receiving a
correct frame, has a fixed, non-zero remainder. The
actual remainder in the receive CRC calculation is
checked against this fixed value to determine if a CRC
error exists.
The contents of the Receive Shift register are
transferred to the receive data FIFO.
The Residue Code is latched, the CRC Error bit is
latched in the status FIFO and the End of Frame bit is set
in the receive status FIFO.
CRC Field
Previous
Byte
SCC™/ESCC™ User’s Manual
Data Communication Modes
4-25
4